1、[ZZ] 关于模拟设计的基本考虑Basic precautions and tips that an Analog Designer should know.1. Minimum channel length of the transistor should be four to five times the minimum feature size of the process. We do it, to make the lambda of the transistor low i.e. the rate of change of Id w.r.t to Vds is lo
2、w.晶体管最小沟长为工艺最小特征尺寸的4-5倍，用来减小沟长调制效应2. Present art of analog design still uses the transistor in the saturation region.So one should always keep Vgs of the Transistor 30% above the Vt.目前模拟设计仍然是使晶体管工作在饱和区，故应使Vgs大于Vt约30%3. One should always split the big transistor into small transistors having
3、width or length feature size应把大管分成小晶体管，使其宽/长特征尺寸<或=15um4. W/L Ratio of transistors of the mirror circuit should be less than or equal to 5, to ensure the proper matching of the transistors in the layout. Otherwise, it results to the Systamatic Offset in the circuit.电流镜电路的晶体管的w/l比应小于或等于5，以保证较
4、好的Matching,否则会有系统失调5. One should make all the required pins in the schmetic before generating the layout view. Because it’s diffcult to add a pin in the layout view. All IO pins should be a metal2 pins whereas Vdd and Ground should be metal1 pins在电路中画出所有的管脚（pin），之后才作layout。因为在layout中增加一个pin是
5、比较困难的。所有的IO pin应该用metal2 pin，Vdd和GND用metal1 pin6. One should first simulate the circuit with the typical model parameters of the devices. Since Vt of the trasistor can be anything between Vt(Typical) -/+ 20%. So we check our circuit for the extreme cases i.e. Vt+20%, Vt-20%. A transistor hav
6、ing Vt-20% is called a fast transistor and transistor having Vt+20% is called slow transistor. It’s just a way to differentiate them. So with these fast and slow transistor models we make four combination called nfpf, nfps, nspf, nsps, which are known as process corners. Now, once we are sat
7、isfied with the circuit performance with typical models than we check it in different process corners, to take the process variation into account. Vt is just one example of the process variation there are others parameter too.首先先用tt做电路仿真。考虑Vt有+20%
