基于VHDL的IIC时序电路设计

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1、基于VHDL的IIC时序电路设计iic总线在设计时要看你所使用的器件的传输或接收时序只要会一个，其他的都一样以下是我在一本书上看到的，你看看就会用了libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityreciverisport(reset,clk:instd_logic;sda,scl:inoutstd_logic;rd:outstd_logic;tdata:instd_l

2、ogic_vector(7downto0);rdata:outstd_logic_vector(7downto0));endreciver;architectureoneofreciverissignalrdatai:std_logic_vector(7downto0);typestateis(start,transmit,ack,sub,ack1,start1,slave,ack2,reading,ack3);signalcurrent:state;beginprocess(clk,reset)variablecount:i

3、ntegerrange0to40;variablecnt:integerrange0to8;beginifreset='1'thensda<='1';scl<='1';rdata<="00000000";current<=start;cnt:=8;count:=0;elsifclk'eventandclk='1'thencasecurrentiswhenstart=>count:=count+1;casecountiswhen1=>sda<='1';when2=>scl<='1';when3=>sda<='0';when4=>

4、scl<='0';when10=>count:=0;current<=transmit;whenothers=>null;endcase;whentransmit=>count:=count+1;casecountiswhen1=>sda<=tdata(cnt);when2=>scl<='1';when3=>scl<='0';when4=>cnt:=cnt-1;count:=0;ifcnt=0thencnt:=8;current<=ack;rd<='1';elsecurrent<=transmit;rd<='0';endif;

5、whenothers=>null;endcase;whenack=>count:=count+1;casecountiswhen1=>sda<='0';when2=>scl<='1';when3=>scl<='0';when4=>current<=sub;count:=0;whenothers=>null;endcase;whensub=>count:=count+1;casecountiswhen1=>sda<=tdata(cnt);when2=>scl<='1';when3=>scl<='0';when4=>cnt:=cn

6、t-1;count:=0;ifcnt=0thencnt:=8;current<=ack1;rd<='1';elsecurrent<=sub;rd<='0';endif;whenothers=>null;endcase;whenack1=>count:=count+1;casecountiswhen1=>sda<='0';when2=>scl<='1';when3=>scl<='0';when4=>current<=start1;count:=0;whenothers=>null;endcase;whenstart1=>coun

7、t:=count+1;casecountiswhen1=>sda<='1';when2=>scl<='1';when3=>sda<='0';when4=>scl<='0';when5=>current<=slave;count:=0;whenothers=>null;endcase;whenslave=>count:=count+1;casecountiswhen1=>sda<=tdata(cnt);when2=>scl<='1';when3=>scl<='0';when4=>cnt:=cnt-1;count:=0;ifcnt

8、=0thencnt:=8;current<=ack2;rd<='1';elsecurrent<=sub;rd<='0';endif;whenothers=>null;endcase;whenack2=>count:=count+1;casecountiswhen1=>sda<