PWM信号发生器的设计程序(veriloghdl)

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1、PWM信号发生器的设计程序modulepwmgen(clk,rst,ce,addr,write,wrdata,read,bytesel,rddata,pwm);inputclk,rst,ce;input[1:0]addr;inputwrite,read;input[31:0]wrdata;output[31:0]rddata;input[31:0]bytesel;outputpwm;reg[31:0]clk_div_reg,duty_cycle_reg;regcontrol_reg;regclk_div_reg_sel,duty_cy

2、cle_reg_sel,control_reg_sel;reg[31:0]pwm_cnt,rddata;regpwm;wirepwm_ena;always@(addr)beginclk_div_reg_sel<=0;duty_cycle_reg_sel<=0;control_reg_sel<=0;case(addr)2'b00:clk_div_reg_sel<=1;2'b01:duty_cycle_reg_sel<=1;2'b10:control_reg_sel<=1;default:beginclk_div_reg_sel<=0;d

3、uty_cycle_reg_sel<=0;control_reg_sel<=0;endendcaseendalways@(posedgeclkornegedgerst)beginif(rst==1'b0)clk_div_reg=0;elsebeginif(write&ce&clk_div_reg_sel)beginif(bytesel[0])clk_div_reg[7:0]=wrdata[7:0];if(bytesel[1])clk_div_reg[15:8]=wrdata[15:8];if(bytesel[2])clk_div_re

4、g[23:16]=wrdata[23:16];if(bytesel[3])clk_div_reg[31:24]=wrdata[31:24];endendendalways@(posedgeclkornegedgerst)beginif(rst==1'b0)duty_cycle_reg=0;elsebeginif(write&ce&duty_cycle_reg_sel)beginif(bytesel[0])duty_cycle_reg[7:0]=wrdata[7:0];if(bytesel[1])duty_cycle_reg[15:8]

5、=wrdata[15:8];if(bytesel[2])duty_cycle_reg[23:16]=wrdata[23:16];if(bytesel[3])duty_cycle_reg[31:24]=wrdata[31:24];endendendalways@(posedgeclkornegedgerst)beginif(rst==1'b0)control_reg=0;elsebeginif(write&ce&control_reg_sel)beginif(bytesel[0])control_reg=wrdata[0];endend

6、endalways@(addrorreadorclk_div_regorduty_cycle_regorcontrol_regorce)beginif(read&ce)case(addr)2'b00:rddata<=clk_div_reg;2'b01:rddata<=duty_cycle_reg;2'b10:rddata<=control_reg;default:rddata=32'h8888;endcaseendassignpwm_en=control_reg;always@(posedgeclkornegedgerst)begin

7、if(rst==1'b0)pwm_cnt=0;elsebeginif(pwm_en)beginif(pwm_cnt>=clk_div_reg)pwm_cnt<=0;elsepwm_cnt<=pwm_cnt+1;endelsepwm_cnt<=0;endendalways@(posedgeclkornegedgerst)beginif(rst==1'b0);elsebeginif(pwm_en)beginif(pwm_cnt<=duty_cycle_reg)pwm<=1'b1;elsepwm<=1'b0;endelsepwm<=1'b0

8、;endendendmodule