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1、IntegratedTestScheduling,TestParallelizationandTAMDesignErikLarsson+∗,KlasArvidsson∗,HideoFujiwara+andZeboPeng∗ComputerDesignandTestLaboratory+EmbeddedSystemsLaboratory∗NaraInstituteofScienceandTechnologyLinköpingsUniversitet8916-5Takayama,Ikoma,Nara630-0101,JapanSE-58283Linköpings,Sweden{er
2、ila,fujiwara}@is.aist-nara.ac.jp{erila,zebpe}@ida.liu.seAbstract1totesttimeandTAMcostatalowcomputationalcost.WehaveanalyzedourpreviousapproachandnotedtheTAMWeproposeatechniqueintegratingtestscheduling,scandesignpartisoflowquality.Furtherfeaturesofourchainpartitioningandtestaccessmechanism(TA
3、M)designproposedapproacharethatwesupport:minimizingthetesttimeandtheTAMroutingcostwhileconsideringtestconflictsandpowerconstraints.Main•testingofuser-definedlogic(UDL),featuresofourtechniqueare(1)theflexibilityinmodelling•testingofunwrappedcores,thesystemstestbehaviourand(2)thesupportfor•mem
4、orylimitationsattestsources,interconnectiontestofunwrappedcoresanduser-defined•bandwidthlimitationsontestsourcesandtestsinks,logic.Experimentsusingourimplementationonseveral•embeddingcoresincore.benchmarksandindustrialdesignsdemonstratethatitWehaveimplementedourtechniqueandperformedseveralpr
5、oduceshighqualitysolutionatlowcomputationalcost.experimentsonbenchmarksincludingalargeEricsson1Introductiondesignwith170tests.Ourtoolanditsmodellingaremadegeneral,whichisanadvantagesinceitcanbeusedtomodelThetestingofSystem-on-Chip(SOC)designsisacrucialthetestbehaviorofnotonlyscantestedsystem
6、s.problemmainlyduetotheincreasingdesigncomplexity,Theorganizationofthepaperisasfollows.Anoverviewwhichleadstohightestdatavolumes.HightestdataofrelatedworkisinSection2andtheconsideredtestvolumesarecausingtotwomajorproblemsdependingonargumentsarediscussedinSection3.Thesystemmodeliseachother;(1
7、)howdesignaminimaltestaccessmechanismdescribedinSection4andourintegratedtestscheduling,(TAM)and(2)howdesignatestscheduleminimizingtesttestparallelizationandTAMdesigntechniqueispresentedtimeundertestconflictsandpowerconstraint.inSection5.Thepaperisc