基于FPGA串口控制器设计中英文翻译

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1、英文原文TheserialcontrollerdesignbasedonFPGAIntroductionTheuseofhardwaredescriptionlanguage(HDL)isbecomingamoredominantfactor,whendesigningandverifyingFPGAdesigns.Theuseofbehaviorleveldescriptionnotonlyincreasesthedesignproductivity,butalsoprovidesuniqueadvantagesinthedesignverification.Themostdo

2、minantHDLstodayarecalledVerilogandVHDL.ThisapplicationnotewillillustratetheuseofVerilogindesignandverificationofadigitalUART(UniversalAsynchronousReceiver&Transmitter).DefiningtheUART.TheUARTconsistsoftwoindependentHDLmodules.Onemoduleimplementsthetransmitter,whiletheothermoduleimplementsther

3、eceiver.Thetransmitterandreceivermodulescanbecombinedatthetoplevelofthedesign,foranycombinationsoftransmitterandreceiverchannelsrequired.Datacanbewrittentothetransmitterandreadoutfromthereceiver,allthroughasingle8bitbi-directionalCPUinterface.Addressmappingforthetransmitterandreceiverchannels

4、caneasilybebuildintotheinterfaceatthetoplevelofthedesign.Bothmodulesshareacommonmasterclockcalledmclkx16.Withineachmodulemclkx16aredivideddowntoindependentbaudrateclocks.UARTfunctionaloverview.AbasicoverviewoftheUARTisshownbelow.Atthelefthandsideisshown“transmitholdregister”,“transmitshiftreg

5、ister”andthetransmitter“controllogic”block,allcontainedwithinthetransmittermodulecalled“txmit”.Attherighthandsideisshownthe“receiveshiftregister”,“receiveholdregister”andthereceiver“controllogic”block,allcontainedwithinthereceivermodulecalled“rxcver”.Thetwomoduleshaveseparateinputsandoutputsf

6、ormostoftheircontrollines,onlythebi-directionaldatabus,masterclockandresetlinesaresharedbybothmodules.TheUARTstandarddataformat.Infigure3isshowntheUARTserialdataformat.Serialdataarecontainedwithinframesof8databits,aswellascodedinformationbits.Betweensuccessivetransmissions,thetransmissionline

7、isheldhigh.Atransmissionisinitializedbyaleadinglowstartbit.Nexttotheleadinglowstartbitcomes8bitsofdatainformation,beginningwiththeLSBandafterwardsrepresentedatincreasingsignificanceorderuptotheMSB.Nexttothe8databitscomestheparitybit,represent