verilog数字系统设计教程第12章例题

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1、第十二章例题[例1]:modulefsm(Clock,Reset,A,K2,KI,state);inputClock,Reset,A;outputK2,KI;outputfl:0]slate;regK2,K1;reg[1:0]state;parameterIdle=2'b00,Start=2'b01,Stop=2'bl0,Clear=2'bl1;always@(posedgeClock)if(!Reset)beginstate<=Idle;K2<=0;KI<=0;endelsecase(state)Idle:if(A)beginstate<=Start;Kl<=0;endelsebeginst

2、ate<=Idle;K2<=0;Kl<=0;endStart:if(!A)state<=Stop;elsestate<=Start;Stop:if(A)beginstate<=Clear;K2<=1;endelsebeginstate<=Stop;K2<=0;Kl<=0;endClear:if(!A)beginstate<=Idle;K2<=0;K1<=1;endelsebeginstate<=Clear;K2<=0;Kl<=0;enddefault:state<=25bxx;endcaseendmodule[例2]:modulefsm(Clock,Reset,A,K2,KI);inputCl

3、ock,Reset,A;outputK2,KI;regK2,K1;reg[3:0]state;parameterIdle=4'blOOO,Start=4'b0100,Stop=4,b()010,Clear=4'b0001;always@(posedgeClock)if(!Reset)beginstate<=Idle;K2<=0;Kl<=0;endelsecase(state)Idle:if(A)beginstate<=Start;Kl<=0;endelsebeginstate<=Idle;K2<=0;Kl<=0;endStart:讦(!A)state<=Stop;elsestate<=Star

4、t;Stop:if(A)beginstate<=Clear;K2<=1;endelsebeginstate<=Stop;K2<=0;Kl<=0;endClear:if(!A)beginstate<=Idle;K2<=0;K1<=1;endelsebeginstate<=Clear;K2<=0;Kl<=0;enddefault:state<=Idle;endcaseendmoduleendmodule[例3]modulefsm(Clock,Reset,A,K2,KI,state);inputClock,Reset,A;outputK2,KI;output[4:0]state;reg[4:0]st

5、ate;assignK2=state[4];//把状态变量的最高位用作输出K2assignKl=state[0];//把状态变量的最低位用作输出K1parameter//K2_i_j_n_K1outputcodedstateassignmentIdle=5'b0_0_0_0_0,Start=5'b0_0_0丄0,Stop=5'b0_0_l_0_0,StopToClear=5'bl」_0_0_0,Clear=5*b01010,ClearToIdle=5fb0_0_l_l_l;always@(posedgeClock)if(!Reset)beginstate<=Idle;endelsecase(s

6、tate)Idle:if(A)state<=Start;elsestate<=Idle;Start:if(!A)state<=Stop;elsestate<=Start;Stop:if(A)state<=StopToClear;elsestate<=Stop;StopToClear:state<=Clear;Clear:if(!A)state<=ClearToIdle;elsestate<=Clear;ClearToIdle:state<=Idle;default:state<=Idle;endcaseendmodule[例4]modulefsm(Clock,Reset,A,K2,KI);in

7、putClock,Reset,A;outputK2,KI;regK2,KI;reg[1:0]state,nextstate;parameterIdle=2*b00,Start=2'b01,Stop=2'blO,Clear=2'bll;//每一个时钟沿产生一次可能的状态变化always@(posedgeClock)if(!Reset)state<=Idle;elsestate<=nextstate;