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1、摘要本设计为一个多功能的数字时钟,具有时、分、秒计数显示功能,以24小时循环计数;具有校对功能。本设计采用EDA技术,以硬件描述语言VerilogHDL为系统逻辑描述语言设计文件,在QUARTUSII工具软件环境下,采用自顶向下的设计方法,由各个基本模块共同构建了一个基于FPGA的数字钟。系统由时钟模块、控制模块、计时模块、数据译码模块、显示以及组成。经编译和仿真所设计的程序,在可编程逻辑器件上下载验证,本系统能够完成时、分、秒的分别显示,按键进行校准,整点报时,闹钟功能。关键词:数字时钟,硬件描述语言,Ve
2、rilogHDL,FPGAAbstractThedesignforamulti-functionaldigitalclock,withhours,minutesandsecondscountdisplaytoa24-hourcyclecount;haveprooffunctionsfunction.TheuseofEDAdesigntechnology,hardware-descriptionlanguageVHDLdescriptionlogicmeansforthesystemdesigndocument
3、s,inQUAETUSIItoolsenvironment,atop-downdesign,bythevariousmodulestogetherbuildaFPGA-baseddigitalclock.Themainsystemmakeupoftheclockmodule,controlmodule,timemodule,datadecodingmodule,displayandbroadcastmodule.Aftercompilingthedesignandsimulationprocedures,th
4、eprogrammablelogicdevicetodownloadverification,thesystemcancompletethehours,minutesandsecondsrespectively,usingkeystocleared,tocalibratingtime.Andontimealarmandclockfordigitalclock.Keywords:digitalclock,hardwaredescriptionlanguage,VerilogHDL,FPGA目录摘要.......
5、.........................................................................................................................1Abstract..............................................................................................................................2
6、第一章绪论................................................................................................................11.1.选题意义与研究现状....................................................................................11.2.国内外研究及趋势.............................
7、...........................................................11.3.论文结构........................................................................................................2第二章编程软件及语言介绍........................................................................
8、............32.1QuartersII编程环境介绍.............................................................................32.1.1菜单栏...................................................................................