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1、A150mALowNoise,HighPSRRLow-DropoutLinearRegulatorin0.13µmTechnologyforRFSoCApplicationsKaeWongandDavidEvansWirelessAnalogTechnologyCenterTexasInstruments,Dallas,TexasUSAAbstract—Anintegratedlow-noise,highpowersupplyrejectiontechnologyalsointroducesmoredesignchallengesduetot
2、heratio(PSRR),low-dropout(LDO)linearregulatorhasbeenlimitationsofthedeep-submicrondevices.ThekeylimitationsdevelopedinTexasInstruments’(TI)130nmCMOStechnology.arelowdeviceoperatingvoltageratingandhighdeviceleakage.TheLDOregulatoriscapableofproducingaregulatedoutputTheprimar
3、ydevicesemployedinthisparticulardesignarethevoltageof2.8VfromaLi-Ionbatterysupply,withadropout1.5Vcoredevicesandthe5Vdrain-extendeddevicesvoltageof200mVwhilesupplyingaloadcurrentof150mA.The(DEMOS).Bothdeviceshavea32Ågateandthegate-to-sourceLDOregulatorfeatures>65dBPSRRat20k
4、Hz,and>40dBupvoltageis1.5Vrated.DEMOSshavea5Vdrain-to-sourceto1MHz.TheLDOregulatoralsofeaturesoutputnoiserating.Thecapacitortypesusedinthisdesigninclude1.5Vandperformanceof<350nVrms/√Hzat100Hz.TheLDOdieareais3.3VdepletedMOSFETcapacitors.20.166mmandthemaximumno-loadpowercons
5、umptionis450µW.III.DESIGNCONSIDERATIONSANDARCHITECTUREI.INTRODUCTIONTheLDOregulatorpresentedisdesignedfornoiseandpowersupplyrejection(PSR)performance.ThefollowingSoCarchitectures,whichnowoftenfeaturepowersectionwilldiscussthearchitectureforthisLDOregulatormanagementfunction
6、alityintegratedwiththeDBB,ABB,anddesigninmoredetail.sometimesRF,presentthecircuitdesignerwithnewchallenges,evenforverywellknowncircuitarchitectures.AsA.PowerFETDesignhigh-voltage,analogfriendlyprocesstechnologiesarereplacedwithdigitallydense,deep-submicrontechnologies,thepo
7、werThepowerFETstructureusedinthisdesignisillustratedmanagementdesignermustadaptcircuittechniqueswithoutinFig.1.ThepowerFETisconstructedbycascodingasacrificingtheintegrityofthedesign.TocomplicatemattersDEPMOSwithacoredevice,wheretheDEPMOSisbiasedbymore,customersareunwillingt
8、orelaxspecifiedtolerancesduePbias.Thecascodedstructureprotectsthecoredevicefromtol
