低功耗标准单元电路设计

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1、低功耗标准单元电路设计4．结合互补静态CMOS结构电路的优点，提出了相应的晶体管级的AND/XOR和OR/XNOR门电路。并在0.13um、0.18um和0.24um三种不同工艺下用HSPICE软件进行了模拟仿真工作，并与相应级联结构进行性能上的分析比较。实验结果表明，提出电路的性能在三种不同工艺下都具有较好的表现。关键词：低功耗，标准单元电路，TraditionalBoolean逻辑，Reed-Muller逻辑，功耗延迟积II万方数据宁波大学硕士学位论文DesignoflowpowerstandardunitcircuitsAbstractWiththerapiddevelopm

2、entofintegratedcircuittechnology,thefeaturesizeshrinkingandthecontinuousimprovementofcircuitintegrationandworkingfrequency,powerconsumptionhasbecomethemainchallengeofintegratedcircuitdesignfollowingspeedandarea.DigitallogiccircuitdesignmethodscanbeclassifiedasAND/OR/NOTbasedTraditionalBoolean(

3、TB)logicandAND/XORbased(orOR/XNOR)Reed-Muller(RM)logic.BecauseTBlogicismoremature,almostallofthecircuitimplementationandcorrespondingEDAtoolsarebasedontheTBlogic.Thecurrentchallengeoftheintegratedcircuitdesignisdeemedpartlycausedbythelogicdesignmethod.ResearchshowsthattheRMlogicisoftheadvantag

4、esinchiparea,speedandpowerforsomecircuits.AlthoughtherearemuchRMlogicresearchinrecentyears,thereisrareresearchonstandardunitcircuitdesign,especiallyinlowpowerstandardcellresearchtargetingRMlogiccircuitdesign.Inthisdissertation,thelowpowerstandardunitcircuitdesigntargetingRMlogicisstudied.Thedi

5、ssertationconsistsofthefollowingaspects:1.ExistingvariousANDgates,XORgates,ORgatesandXNORgatesareanalyzedandthecascadeAND/XORsandOR/XNORgatesareascomparativeobjectsagainsttheproposedcircuitsbasedontransistorlevel.2.DuetotheadvantagesofPassTransistorLogic(PTL)andTransmissionGate(TG)Logic,propos

6、edthetransistorlevelAND/XORandOR/XNORGatesareproposed.3.UndertheLinux,55nmprocessenvironment,theCadencetoolsareusedtocarryouttheschematicandlayoutdesignfortheproposedcircuits.TheCalibretoolisusedtodoDRC,LVSandtheparasiticparameterextraction.HSPICEisemployedtosimulatethecircuitperformanceandcom

7、parisonismadeagainstthecascadedcircuits.TheexperimentalresultsshowthattheimprovementoftheproposedAND/XORgatecircuitpowerconsumptionandthepowerdelayproduct(PDP)isashighas26.67%and31.25%respectively.WhiletheOR/XNORgateisashighas21.88%and3