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1、TheVerilogHardwareDescriptionLanguageProfessorDonThomasCarnegieMellonUniversity(CMU)thomas@ece.cmu.eduhttp://www.ece.cmu.edu/~thomasnThisisnotonecohesivepresentationonVerilog.TheslidescontainedherearecollectedfromdifferentCMUclassesatvariousacademiclevels.nTheseslidesareprovidedasanalternateai
2、dtolearningthelanguage.Youmayfindthemhelpful.nSendbugreportstotheaboveaddress—therearesome!nTheVerilogHardwareDescriptionLanguage,FourthEditionisavailablefromKluwerAcademicPublishers,http://www.wkap.com.Phone:781-871-6600.nUniversityfacultywantingaccesstoaPowerPointversionoftheslidesshouldcont
3、acttheauthorattheaboveaddress.©DonThomas,1998,11SimulationofDigitalSystemsnSimulation—lWhatdoyoudototestasoftwareprogramyouwrite?-Giveitsomeinputs,andseeifitdoeswhatyouexpect-Whendonetesting,isthereanyassurancetheprogramisbugfree?—NO!-But,totheextentpossible,youhavedeterminedthattheprogramdoes
4、whatyouwantittodolSimulationtestsamodelofthesystemyouwishtobuild-Isthedesigncorrect?Doesitimplementtheintendedfunctioncorrectly?Forinstance,isitaUARTlStickinabyteandseeiftheUARTmodelshiftsitoutcorrectly-Also,isitthecorrectdesign?lMighttherebesomeotherfunctionstheUARTcoulddo?©DonThomas,1998,22S
5、imulationofDigitalSystemsnSimulationcheckstwopropertieslfunctionalcorrectness—isthelogiccorrect-correctdesign,anddesigncorrectltimingcorrectness—isthelogic/interconnecttimingcorrect-e.g.aretheset-uptimesmet?nIthasallthelimitationsofsoftwaretestinglHaveItriedallthecases?lHaveIexercisedeverypath
6、?Everyoption?©DonThomas,1998,33ModernDesignMethodologySimulationandSynthesisarecomponentsofadesignmethodologyalwaysmumbleSynthesisgates,gates,gates,…mumbleblahblahSynthesizableVerilogTechnologyMappingPlaceandRouteclb1clb2©DonThomas,1998,44Representation:StructuralModelsnStructuralmodelslArebui
7、ltfromgateprimitivesand/orothermoduleslTheydescribethecircuitusinglogicgates—muchasyouwouldseeinanimplementationofacircuit.-Youcoulddescribeyourlab1circuitthiswaynIdentify:lGateinstances,wirenames,delayfromaorbtof.modulemux(f,a,b,sel);a
