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页数:4页
时间:2019-02-28
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1、ModelingandVerificationofHigh-SpeedWiredLinkswithVerilog-AMSMing-taHsiehGeraldE.SobelmanDepartmentofElectricalandComputerEngineeringDepartmentofElectricalandComputerEngineeringUniversityofMinnesotaUniversityofMinnesotaMinneapolis,MN55455,USAMinneapolis,MN5545
2、5,USAmthsieh@umn.edusobelman@umn.eduAbstract—Behavioralmodelingwithvirtualbuilt-inself-testtimethatwouldberequired[4].Usingbehavioralmodelingverificationofhigh-speedwiredlinkdesignsisdescribedinthisletsdesignerseasilyexploredifferentsystem-levelarchitec-paper
3、.Ourprocedureisbasedonprinciplesoftop-downturesattheearlydesignstagesandtherebyrapidlyperformmixed-signaldesigncombinedwithabehavioraldescriptionsystem-levelverification,Thus,includingbehavioralmodelslanguageandmixed-modesimulations.TheuseofVerilog-intheovera
4、lldesignprocessreducestimetomarketandAMSisappliednotonlytocircuitmodelingbutalsoforrepre-helpstoensurefirsttimecorrectsilicon.sentingnoiseontheinputsignal.Thisapproachprovidessys-tem-leveljittertoleranceestimation,circuitcriticalpathsearchClockwithJitterModel
5、ingandoveralldesignverification.Codingexamplesandsimula-ParallelReferenceParallelDataOutputClockInputDataInputtionresultsareincluded.PRBSDatawithJitterModelingClockDeserializerSerializerSynthesizerI.INTRODUCTIONTheideaoftop-downmixed-signalcircuitdesignusinga
6、ClockandDataDataVerificationRecoverybehavioraldescriptionforsystem-levelmodelinghasbeenaCriticalPathDetectiontopicofresearchinterest[1-3].Typically,systemarchitec-ReceiverTransmitterturedesignersderivetherequiredsystemorcircuitspecifica-InputBufferOutputBuffe
7、rtionforcertaintargetedapplications.Ontheotherhand,withEqualizerwithPre-emphasiscircuitdesignerswouldsearchforatypeofcircuitwhichisDataVerificationthebestfitfortherequiredspecificationswithminimumTransmissionChannelEye-OpeningMonitoringISI,Random,andSinusoida
8、ldesigncostandtimeandhavingsuperiorperformance.Be-JitterGenerationforegoingaheadwiththedetailedtransistor-leveldesign,TransmitterReceiverbehavioralmodelsareusuallyusedtoverifythedesignatt
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