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1、DisplayPortOverview•DisplayPortisthenewdigitaldisplayinterfacestandard.•PromotergroupconsistsofDELL,HP,Intel,GenesisMicrochip,Samsung,Philips,ATI,NVidia,Tyco,Molex•VESAtopublishandmaintainthestandards•DisplayPortwillinitiallyreplaceDVIinterfacesinPC.2100年7月26日星期二DisplayPortOverview•MainLink•H
2、igh-bandwidth,low-latency,unidirectional•Isochronousstreamtransport•AUXCH(AuxiliaryChannel)•Consistentbandwidth,low-latency,bi-directional•MainLinkmanagement,Devicecontrol(EDID,MCCS)•HPD(HotPlugDetect)•AlsousedasInterruptRequestLinkrate:Either2.7Gbpsor1.62Gbpsperlane•De-coupledfromPixelRate•D
3、ependsonTx/RxcapabilityandChannelquality3100年7月26日星期二LinkStructure-MainLink•1,2,or4lanes•De-coupledfromPixelBitDepth»Supports6,8,10,12,and16bpc(bitspercomponent),inRGB,YCbCr444/422colorimetryformatsinVer.1.0»Easilyextendedtoanyrequiredbitdepthorcolorimetry•Alllanescarrydata(nodedicatedclockla
4、ne)»ClockextractedfromANSI8B/10Bencodeddatastream»Noreferenceclockrequiredinthereceiver»DatasymbolsscrambledforEMIreduction»Optionalsupportofspread-spectrumforfurtherEMIreduction•Lanecountrequirement»SourceandSinkdevicesallowedtosupportminimumnumberoflanesrequiredfortheirneeds»Externalcable-c
5、onnectorassemblyrequiredtosupport4lanes4100年7月26日星期二LinkStructure-AuxCH•Half-duplex,bi-directionalchanneloverAC-coupled,differentialpair•Self-clockeddatasignal(ManchesterIIchannelcoding)•Source=Master,Sink=Slave»SinksendsIRQ(InterruptRequest)viaHPDline•Consistentbitrateovervariouscablelengths
6、(15mandbeyond)•1Mbits/sec•Minimallatency•Maximumtransactionperiod<500us»Burstdatasizeequaltoorlessthan16Bytes»PreventsoneAUXCHapplicationfromstarvingothers•EasyinteroperationwithDDClegacy•SimpleprotocolbridgingtoDDC5100年7月26日星期二LinkStructure–HotPlugDetect•LinkandDeviceServicesforPlug&Play•Est
7、ablishesthelinkuponHot-PlugDetection•TransmitterreadsDPCDofReceiver•LinkconfiguredthroughLinkTraining»Propernumberoflanesenabledatproperlinkrateforagivenapplicationwithproperequalizationlevel•Linkstatusmonitored»ViaIRQsignalonHPDlineassertedb
