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ID:33486704
大小:1.13 MB
页数:24页
时间:2018-05-23
《微处理器接口芯片设计实例可编程并行接口芯片设计实例ppt培训课件》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、第十三讲微处理器接口芯片设计实例--可编程并行接口芯片设计实例曲阜师范大学电气信息与自动化学院本讲主要内容8255的引脚及内部结构8255的工作方式及其控制字8255的结构设计8255芯片的VHDL语言描述8255芯片VHDL语言描述模块仿真8255的引脚及内部结构外部引脚内部结构控制字LIBRARYIEEE;USEIEEE.STD_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPPIIS使用库PORT(RESET,RD,WR,CS,A0,A1:INST
2、D_LOGIC;PA:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);PB:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);PCL:INOUTTD_LOGIC_VECTOR(3DOWNTO0);PCH:INOUTSTD_LOGIC_VECTOR(3DOWNTO0);D:INOUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDPPI;实体描述构造体描述ARCHITECTURERTLOFPPIISSIGNALINTERNAL_BUS_OUT:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALIN
3、TERNAL_BUS_IN:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALST,AD,FLAG:STD_ULOGIC_VECTOR(1DOWNTO0);SIGNALCTRREG:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALPA_LATCH,Pb_LATCH,Pc_LATCH:CTRREG:STD_ULOGIC_VECTOR(7DOWNTO0);读进程BEGINPROCESS(RD,CS)Beginst<=cttreg(3)&cttreg(0);if(cs=‘0’andrd=‘0’)thenif(a0=‘0’an
4、da1=‘0’andcttreg(4)=‘1’)theninternal_bus_in<=pa;elsif(a0=‘0’anda1=‘0’andcttreg(1)=‘1’)theninternal_bus_in<=pb;elsif(a0=‘0’anda1=‘1’andst=“01”)theninternal_bus_in(3downto0)<=pcl(3downto0);elsif(a0=‘0’anda1=‘1’andst=“10”)theninternal_bus_in(7downto4)<=pch(3downto0);elsif(a0=‘0’anda1
5、=‘1’andst=“11”andctrreg(7)=‘1’)theninternal_bus_in(3downto0)<=pcl(3downto0);internal_bus_in(7downto4)<=pch(3downto0);process(cs,wr,reset)variablectrregF:std_ulogic;variablebctrreg_v:std_ulogic_vector(3downto0);beginif(cs='0'andwr='0')thenad<=a1&a0;ctrregF:=d(7);iternal_bus_out<=d;
6、endif;if(reset='1')thenpa_latch<="00000000";pb_latch<="00000000";pc_latch<="00000000";ctrreg<="10011011"bctrreg_v:="0000";ctrregF:='0';elsif(wr'eventandwr='1')thenif(ctrregF='1'andad="11"andcs='0')thenctrreg<=internal_bus_out;elsif(ctrreg(7)='1'andad="00"andcs='0')thenpa_latch<=in
7、ternal_bus_out;elsif(ctrreg(7)='1'andad="01"andcs='0')thenpb_latch<=internal_bus_out;elsif(ctrreg(7)='1'andad="10"andcs='0')thenpc_latch<=internal_bus_out;elsif(ctrregF='0'andad="11"andcs='0')thenbctrreg:=internal_bus_out(3downto0);casebctrreg_viswhen"0000"=>pc_latch(0)<='0';when"
8、0010"=>pc_latch(1)<='0';when"0100
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