飞思卡尔双核单片机的超频源代码及注释(xs128)

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1、＃include     /*commondefinesandmacros*/＃include    /*derivativeinformation*/#pragmaLINK_INFODERIVATIVE"mc9s12xs128"voiddelayms(intms){     intii,jj;  if(ms<1)ms=1;  for(ii=0;ii

2、SEL=0X00;    //disengagePLLtosystem   PLLCTL_PLLON=1;   //turnonPLL   SYNR=0x00

3、0x01; //VCOFRQ[7:6];SYNDIV[5:0]                       //fVCO=2*fOSC*(SYNDIV+1)/(REFDIV+1)                       //fPLL=fVCO/(2×POSTDIV)                        //fBUS=fPLL/2                        //VCOCLKFrequen

4、cyRanges VCOFRQ[7:6]                       //32MHz<=fVCO<=48MHz   00                       //48MHz< fVCO<=80MHz   01                       //Reserved                 10                       //80MHz< fVCO<=120MHz  11       REFDV=0x80

5、0x01; //REFFRQ[7:6];REFDIV[5:0]                       //f

6、REF=fOSC/(REFDIV+1)                       //REFCLKFrequencyRanges REFFRQ[7:6]                       //1MHz<=fREF<= 2MHz      00                       //2MHz< fREF<= 6MHz      01                       //6MHz< fREF<=12MHz      10                       //fREF> 12MHz              11            

7、                                    //pllclock=2*osc*(1+SYNR)/(1+REFDV)=32MHz;   POSTDIV=0x00;      //4:0,fPLL=fVCO/(2xPOSTDIV)                       //IfPOSTDIV=$00thenfPLLisidenticaltofVCO(dividebyone).   _asm(nop);         //BUSCLOCK=16M   _asm(nop);   while(!(CRGFLG_LOCK==1));  //whenpl

8、lissteady,thenuseit;   CLKSEL_PLLSEL=1;         //engagePLLtosystem; }voidSetBusCLK_32M(void){      CLKSEL=0X00;    //disengagePLLtosystem   PLLCTL_PLLON=1;   //turnonPLL   SYNR=0x40

9、0x03; //pllclock=2*osc*(1+SYNR)/(1+REFDV)=64MHz;                         REFDV=0x80

10、0x01;    POSTDIV=0x00;  

11、   _asm(nop);         //BUSCLOCK=32M   _asm(nop);   while(!(CRGFLG_LOCK==1));  //whenpllissteady,thenuseit;   CLKSEL_PLLSEL=1;         //engagePLLtosystem; }voidSetBusCLK_40M(void){      CLKSEL=0X00;    //disengagePLLtosystem   PLLCTL_PLLON=1;   //turnon