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1、9&荽郑宅智皖Verilog实验报告题目:JK触发器、同步计数器通信工程通信工程系部名称:专业名称:班级:班内序号:学生姓名:2010.11.28实验内容:用JK触发器构成同步计数器:设计一个同步计数器,其逻辑图和JK触发器的逻辑图所示。清零信号clear低电平有效,输入数据在时钟信号clock的上升沿被锁存,触发器在clock的下降沿输出,当count_enable信号为低电平时停止计数。写出同步计数器的verilog描述和激励模块,在激励模块屮使用clear和count.enable对计数器进行测试,并显示输出计数Q[3:0]。二、实验原理图
2、:图6.5qbar0UIQl?lQJKJHEZ图6“网位带渝富対和计数粳能瑞•的同步比数霜JK触发器构成同步计数器源代码:〃主模块modulesynchronous_counter(clear,clock,count_enable,Q);inputclear,clock,count_enable;output[3:0]Q;wireqbarl,qbar2,qbar3,qbarO;wirea,b,c;assigna=Q[0]&count_enable;assignb二a&Q[l];assignc二b&Q⑵;JK_flip_flopmyJK(count
3、_cnable,count_cnable,clock,clear,Q[0],qbarO);JK_flip_flopmyJKl(a,a,clock,clear,Q[l],qbarl);JKflipflopmyJK2(b,b,clock,clear,Q[2],qbar2);JKflipflopmyJK3(c,c,clock,clear,Q[3],qbar3);endmodule//调用的JK触发器模块moduleJK_flip_flop(j,k,clock,clear,q,qbar);inputj,k,clock,clear;outputq,qbar
4、;wirea,b,y,ybar,c,cbar,d,q,qbar;assigna二~(((qbar&j)&clock)&clear);assignb二~((clock&k)&q);assigny=(a&ybar);assignybar=((y&clear)&b);assignc二~(y&cbar);assigncbar二~clock;assignd二~(cbar&ybar);assignq=~(c&qbar);assignqbar=((q&clear)&d);endmodule测试文件源代码:modulecount_test;regcount_en
5、able=l,clock二0,clear=0;wire[3:0]Q;synchronous_countermyCount(clear,clock,count_enable,Q);initial#10clear=l;always@(negedgeclock)begin$monitor($time,,zclear=%b,count_enable=%b,Q=%b%b%b%b,z,clear,count_enable,Q[3],Q[2],Q[l],Q[0]);endalwaysclock二#5"clock;alwayscount_enable=#17
6、0~count_enable;cndmodulc实验结果:0clear=0,counLenable=1zQ=000010clear=1,counLenable=1,Q=000020clear=1,counLenable=1,Q=000130clear=1,counLenable=1,Q=001040clear=1,counLenable=1,Q=001150clear=1,counLenable=1,Q=010060clear=1,counLenable=1,Q=010170clear=1,counLenable=1,Q=011080clear=
7、1,counLenable=1,Q=011190clear=1,counLenable=1,Q=1000100clear=1zcount_enable=1ZQ=1001110clear=1zcount_enable=1卫=1010120clear=1zcounLenable=1,Q=1011130clear=1zcounLenable=1,Q=1100140clear=1zcount_enable=1ZQ=1101150clear=1zcounLenable=1,Q=1110160clear=1zcounLenable=1,Q=1111170cl
8、ear=1zcounLenable=0,Q=0000180clear=1zcounLenable=OzQ=0000波形图:■nr丄k.j