5、MHzisthesysclk,50_000_000=2FAF080
always@(posedgeclk_in)
begin
counter<=counter+1;
if(counter==cnt/2-1)
begin
clk_out<=!clk_out;
counter<=0;
end
end
endmodule
//主程序
moduleJTD(clk,led);
inputclk;
output[7:0]led;
reg[7:0]led;
reg[4:0]state;
always@(posedgeclk)
beginstate=state+5'b00001;
case(sta