基于vhdl语言数字频率计的设计说明书

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1、关于数字频率计设计[摘要]本报告介绍了一种以大规模可编程逻辑芯片为设计载体，由顶到底分层设计，多功能数字频率计的设计方法。该频率计采用VHDL语言程序与原理图相结合的方法，极大地减少了硬件资源占用。该数字频率计测量范围为0到9999HZ，基准频率为1HZ，结果用4只7段数码管显示十进制结果。中间用到了设置控制电路、计数电路、锁存电路和译码电路等模块。仿真结果表明，该数字频率计性能优异，设计语言灵活，硬件更简单，速度更快。[关键词]数字频率计；控制电路；计数电路；锁存电路-I-Withregardtothedesignofdigitalfrequencymeter[Abst

2、ract]Thepresentreportdescribesalarge-scaleprogrammablelogicchipdesigncarrier,intheendbyatop-tiereddesign,multi-functiondigitalfrequencymeterdesignmethods.ThefrequencycounterusingVHDLlanguageprograms,andthemethodofcombiningschematic,greatlyreducingthehardwarefootprint.Thedigitalfrequencyme

3、termeasurementrangefrom0to9999HZ,thebasefrequencyof1HZ,theresultswiththefour7-segmentLEDdisplaydecimalresults.Intermediateusedforsettingupcontrolcircuit,countingcircuit,latchcircuitanddecodingcircuitmodules.Thesimulationresultsshowthatthedigitalfrequencymeterhigh-performance,designlanguag

4、eflexibility,hardwaresimplerandfaster.[Keywords]digitalfrequencymeter;controlcircuit;countingcircuit;LatchCircuit-II-通信工程专业课程设计Ⅱ目录摘要...................................................................................................................IAbstract.................................

5、............................................................................II第1章引言.......................................................................................................3第2章VHDL的简述......................................................................................42.1VH

6、DL的发展.......................................................................................42.2VHDL的特点.......................................................................................42.3VHDL语言结构...................................................................................42.3

7、.1实体（ENTITY）....................................................................52.3.2结构体（ARCHITECTURE）.................................................62.4VHDL软件设计简介...........................................................................6第3章频率计方案的设计.............