仿真中是利用modelsim软件的自带加载仿真数据功能实现的仿.doc

《仿真中是利用modelsim软件的自带加载仿真数据功能实现的仿.doc》由会员上传分享，免费在线阅读，更多相关内容在行业资料-天天文库。

1、1、仿真中是利用modelsim软件的自带加载仿真数据功能实现的仿真。所以没有编仿真数据文件。数据流依次是（47）01000111001100110110011011001100。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYframeISPORT(clk:INSTD_LOGIC;data:INSTD_LOGIC_vector(0to7);syna:OUTSTD_LOGIC);ENDframe;ARCHITECTUREbehaviorOFframeISTYPEstateIS(s0,

2、s1,s2,s3,s4);SIGNALs,next_s:state;记录状态SIGNALd:STD_LOGIC_vector(0to7);描述数据流SIGNALnum:INTEGERRANGE0TO15;num用来找到祯头计数祯长的SIGNALevenorodd:STD_LOGIC;记录是否找到祯SIGNALadd:INTEGERRANGE0TO2;记录出错次数BEGINPROCESS(clk,data)逐字节找祯头BEGINIF(next_s/=s0)andrising_edge(clk)THENIFnum=15THENn

3、um<=0;ELSEnum<=num+1;ENDIF;d<=data;ELSIFrising_edge(clk)THENd<=data;ENDIF;ENDPROCESS;PROCESS(next_s)状态转换BEGINs<=next_s;ENDPROCESS;process(clk)进入状态机BEGINIFclk'eventANDclk='1'THENCASEsISWHENs0=>IFd="01000111"THENnext_s<=s1;syna<='0';evenorodd<='1';ELSEnext_s<=s0;syna

4、<='0';evenorodd<='0';ENDIF;WHENs1=>syna<='0';IFnum=15THENIFd="01000111"THENnext_s<=s2;evenorodd<='1';ELSEnext_s<=s0;syna<='0';evenorodd<='0';ENDIF;ENDIF;WHENs2=>IFnum=15THEN找到三祯，准备进入s3同步态IFd="01000111"THENnext_s<=s3;syna<='0';evenorodd<='1';ELSEnext_s<=s0;syna<='0'

5、;evenorodd<='0';ENDIF;ENDIF;WHENs3=>syna<='1';IFnum=15THENIFd="01000111"THENnext_s<=s4;evenorodd<='1';add<=0;ELSEifadd=2then如果发现第三祯仍旧next_s<=s0;出错，回到s0初态syna<='0';evenorodd<='0';elseadd<=add+1;next_s<=s4;syna<='1';evenorodd<='0';endif;endif;endif;WHENs4=>IFnum=15TH

6、ENIFd="01000111"THENnext_s<=s3;syna<='1';evenorodd<='1';add<=0;ELSEifadd<=1thennext_s<=s0;syna<='0';evenorodd<='0';elseadd<=add+1;next_s<=s4;syna<='1';evenorodd<='0';endif;endif;endif;ENDCASE;ENDIF;ENDPROCESS;ENDARCHITECTURE;基于FPGA的数字系统设计_课程设计(题目附后)1、程序实现了在ts_in输入‘

7、47’‘1F’‘FF’时将din的值加入tsout的目的（见源码后仿真结果图）。结果正确。1、其中din的输入值需要另外设置buffer中给予缓冲，在空祯到来时按照先入先出的原则输入到ts_out中，但因时间，和资料有限，试过多次总会出些其他错误，未能实现。因此仅将din输入的值在空祯到来时填入tsout的空位。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYadd_stringISPORT(ts_out:OUTstd_logic_vector(7downto0));ENDadd_s

8、tring;ARCHITECTUREadd_inOFadd_stringISsignalsyna,reset:STD_LOGIC;signalts_in,din:std_logic_vector(7downto0);SIGNALclk:STD_LOGIC:='1';SIGNALadd:ST