武汉理工大学eda实验

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1、实验1-11920libraryIEEE;21useIEEE.STD_LOGIC_1164.ALL;22useIEEE.STD:LOGIC:ARITH“ALL;23useIEEE.STD:LOGIC:UNSIGNED.ALL;24一一25Unconurencthefollowinglibrarydeclarationifinstantiating26anyXilinxprimitivesinthiscode.27—-libraryUNISIM;28--useUNISIM.VComponents.all;2929entityCounter^is30Port(a:inSTD_LOGIC;31b

2、:inSTD_LOGIC;32c:inSTD:LOGIC;33z:out5TD—LOGIC);34endCounter4;3635architectureexpressionofCounter4is3836begin37z<=(notaandb)or(aandc);4138endexpression;43CurrentSimulationTime:1000ns)ns100ns200IIIII■II■IW1.ns300ns111111111400ns500ns600ns700111L11■■11111111ns800111111ns900ns1000nsIIIIIIIII0/>30tj1q/

3、!c1r1II■实验1-21920libraryIEEE;21useIEEE.STD_LOGIC_11€4.ALL;22useIEEE.STD:LOGIC:ARITH.ALL;23useIEEE.STD:LOGIC:UNSIGNED.ALL;24_25Uncoinmentthefollowinglibrarydeclarationifinstantiating26anyXilinxprimitivesinthiscode.27—libraryUNISIM;28——useUNISIM.VComponents.all;2929entityAlladderis30Port(a:in5TD_LOG

4、IC;31b:inSTD:LOGIC;32Cin:inSTD_LOGIC;33Sum:outSTD—LOGIC;34Cout:outSTD_LOGIC);35endAlladder;373SarchitectureconcurrentofAlladderis3940begin41^>Sum<=axorbxorCin;42Cout<=(aandb)or(aandCin)or(bandCin);43[>endarchitectureconcurrent;实验2-120libraryIEEE;21useIEEE.STD_LOGIC_1164.ALL;22useIEEE.numericstd.al

5、l;23_24Uncommentthefollowinglibrarydeclarationifinstantiating25anyXilinxprimitivesinthiscode.26—libraryUNISIM;27--useUNISIM.VCoirtponencs.all;2828entitydecoderis29Port(a:inSTD_LOGIC_VECTOR(2downto0);30z:outSTD_LOGIC一VECTOR(7downto0));31enddecoder);3332architecturerotateofdecoderis33constantz_out:B

6、IT_VECTOR(7downto0):=(0=>*11rothers=>101);34begin35z<=to_StdLogicVector(z_outsllto_ir.teger(unsigned(a)));36-37endrotate;CurrentSimulationlime:1000nsDn$100ru200II1II1IIIns300n$400ru500ns600ns700ns80005900ns1G00nsI1LIIII■皿1丄1J1J11I1J1■_1J■11■1l11J1□Wa(2:0)3H5「3加—；:■(31)1X3112/11糾训0L1qJIa(0]111Co944

7、7:0]8D2001JZ糾棚011L4I!4511il!44]04I.»43l0ql.»4210if!4110測0实验2-23031323334entitydecoder2isPort(a:iny:outValid:enddecoder2;STD_LOGIC_VECTOR(3downto0);STD_LOGIC_TCTOR(1downto0);out_STD_LOGIC);3536[^architectureitera