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时间:2018-10-31
《华科微机原理实验报告》由会员上传分享,免费在线阅读,更多相关内容在工程资料-天天文库。
1、微机原理实验报告课程:微机原理指导老师姓名:学号:实验名称:Lab02:MIPS处理器部件实现A微机原理实验报告专业:班级:曰期:2013.10.19成绩:学生姓名(签名)指导教师(签名)一、实验目的木实验旨在实现MIPS处理器的部件一控制器和ALU,理解CPU控制器,理解ALU的原理,使用Verilog语言设计CPU控制器和ALU,使用ISim进行行为仿真。二、实验原理及说明MIPS的基本染构如图1所示,柄Control,ALU这样的纽合巡輯中元,也柄如instructionmemory,Datamemo
2、ry和Registersfile打储单■元。本次脸主要次现CPUControl和ALU两个部分《>(一)CPU控制器的实现MimpBranchMemRodMtrrtoRegM3、单元的译码,给ALU,DataMemory,Registers,Muxs等部件输出正确的控制信号。opcodersrtrdshamtfunct312625212016151110653opcodersrtimmediate312625212016153opcodedUUIC»76753阁2.MIPS蓝木指令格式InputoroutputSignalnameReformat1wswbeqInputs—0—I1—e—Op400ccOp3001cOp2GiOpi011cOpO011cOutputsRegDsi磉丄4、QAAALLSrc011cMemtoReg01XXKegWnte1钃外uLMemRead01qcMemWrit©00lcBranch00c1ALLOpl1pqcALLOpO0001注:Jump指令编码足000010,Jump输出信兮为1,其他输出信号都为0图3.Opcode与控制输出的编码关系I冬5、4.Funct,ALUOp与ALUControl编码关系InstructionALUOpInstructionFunctfieldDesiredALUcontrolibIHflLW00loadwordX)(XXX6、Xadd0010sw00storewordxxxxxxadd0010Branchequal01branchequalxxxxxxsubtract0110R-type10add100000add0010R4ype10subtract1000100110R-type10AND100100and0000Rtypc10OR1001C1or0001R-type10setonlessthan101010setonlessthan0111(二}ALU的实现ALU是CPU核心的计算单元,实现诸如加,减,或,与等操作。ALU7、controllinesFunction0000AND0001OR0010add0110subtract0111setonlessthan1100NOR算术操作的编码三、实验verilog代码(一)CPU控制器的实现moduleCtr(input[5:0]OpCode,input[5:0]Fund,outputregKegDst,outputregALUSrc,outputregRegWrite,outputregMemWrite,outputrcgMcmRcad,outputreg.MemtoKeg,ou8、tputregBranch,outputregJump,outputreg[3:0]ALUControl);reg[1:0]ALUOp;always@(OpCode)begincase(OpCode)//Rtype6’bOOOOOO:beginKegDst二1;ALUSrc=0:RcgWrite=l;MernWrite=O;McmRcad=0;•MemtoKeg二0:Branch=0;AIX0p=2’bl0;Jump=0;end//beq6’bOOOlOO:beginRegDst=l’bx;ALUSrc=09、:KegWrite二0:MemWrite=0;McmRead=0;MemtoReg=rbx;Branch=l;ALUOp二2’bOl;Jump=0;end//lw6’bl00011:beginKegDst二0;ALUSrc=l;RcgWrite=l;MernWrite=0;McmRcad=l;MeratoReg=l;Branch=0;AIX0p=2,bOO;Jump=0;end//sw6’bl01011:begi
3、单元的译码,给ALU,DataMemory,Registers,Muxs等部件输出正确的控制信号。opcodersrtrdshamtfunct312625212016151110653opcodersrtimmediate312625212016153opcodedUUIC»76753阁2.MIPS蓝木指令格式InputoroutputSignalnameReformat1wswbeqInputs—0—I1—e—Op400ccOp3001cOp2GiOpi011cOpO011cOutputsRegDsi磉丄
4、QAAALLSrc011cMemtoReg01XXKegWnte1钃外uLMemRead01qcMemWrit©00lcBranch00c1ALLOpl1pqcALLOpO0001注:Jump指令编码足000010,Jump输出信兮为1,其他输出信号都为0图3.Opcode与控制输出的编码关系I冬
5、4.Funct,ALUOp与ALUControl编码关系InstructionALUOpInstructionFunctfieldDesiredALUcontrolibIHflLW00loadwordX)(XXX
6、Xadd0010sw00storewordxxxxxxadd0010Branchequal01branchequalxxxxxxsubtract0110R-type10add100000add0010R4ype10subtract1000100110R-type10AND100100and0000Rtypc10OR1001C1or0001R-type10setonlessthan101010setonlessthan0111(二}ALU的实现ALU是CPU核心的计算单元,实现诸如加,减,或,与等操作。ALU
7、controllinesFunction0000AND0001OR0010add0110subtract0111setonlessthan1100NOR算术操作的编码三、实验verilog代码(一)CPU控制器的实现moduleCtr(input[5:0]OpCode,input[5:0]Fund,outputregKegDst,outputregALUSrc,outputregRegWrite,outputregMemWrite,outputrcgMcmRcad,outputreg.MemtoKeg,ou
8、tputregBranch,outputregJump,outputreg[3:0]ALUControl);reg[1:0]ALUOp;always@(OpCode)begincase(OpCode)//Rtype6’bOOOOOO:beginKegDst二1;ALUSrc=0:RcgWrite=l;MernWrite=O;McmRcad=0;•MemtoKeg二0:Branch=0;AIX0p=2’bl0;Jump=0;end//beq6’bOOOlOO:beginRegDst=l’bx;ALUSrc=0
9、:KegWrite二0:MemWrite=0;McmRead=0;MemtoReg=rbx;Branch=l;ALUOp二2’bOl;Jump=0;end//lw6’bl00011:beginKegDst二0;ALUSrc=l;RcgWrite=l;MernWrite=0;McmRcad=l;MeratoReg=l;Branch=0;AIX0p=2,bOO;Jump=0;end//sw6’bl01011:begi
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