vhdl设计ad转换状态机

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1、libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityadreadisport(ad_data_in:instd_logic_vector(11downto0);reset:instd_logic;clk_50mhz:instd_logic;ad1_eoc_in:instd_logic;ad1_eolc_in:instd_logic;convst:outstd_logic;cs:outstd_logic;rd:outstd_log

2、ic;fifo_wr:outstd_logic;fifo_cs:outstd_logic;fifo_ifclk:outstd_logic;fifo_data:outstd_logic_vector(15downto0);fifo_address:outstd_logic_vector(1downto0));endadread;architectureartofadreadissignalad_convst_wait_start:std_logic;signalad_convst_wait_end:std_logic;signa

3、lad_convst_start:std_logic;signalad_convst_end:std_logic;signalread_ad_state:std_logic_vector(4downto0);signaleoc_count_eight_start:std_logic;signaleoc_count_eight_end:std_logic;signalad_read_start:std_logic;signalad_read_end:std_logic;signalfifo_tran_start:std_logi

4、c;signalfifo_tran_end:std_logic;signalad_convst_wait_count:std_logic_vector(15downto0);signalad_convst_count_reg:std_logic_vector(2downto0);signalad1_convst:std_logic;signaleoc_count_reg:std_logic_vector(2downto0);signalad1_eoc_reg:std_logic;signalad_read_clk:std_lo

5、gic;signalad_read_data_state:std_logic_vector(4downto0);signalad_read_delay_reg:integer;signalad1_cs:std_logic:='1';signalad_data_ch1,ad_data_ch2,ad_data_ch3,ad_data_ch4:std_logic_vector(11downto0);signalad_data_ch5,ad_data_ch6,ad_data_ch7,ad_data_ch8:std_logic_vect

6、or(11downto0);signalifclk_reg:std_logic:='1';signalfifo_wr_reg:std_logic:='1';signalfifo_tran_state:std_logic_vector(4downto0):="00000";signalfifo_data_reg:std_logic_vector(15downto0);beginload1:process(clk_50mhz,reset)beginif(clk_50mhz='1'andclk_50mhz'event)thenif(

7、reset='0')thenad_convst_wait_start<='0';ad_convst_start<='0';ad_read_start<='0';fifo_tran_start<='0';read_ad_state<="00000";elsecaseread_ad_stateiswhen"00000"=>ad_convst_wait_start<='0';ad_convst_start<='0';ad_read_start<='0';fifo_tran_start<='0';read_ad_state<="000

8、01";when"00001"=>if(ad_convst_wait_end='1')thenad_convst_wait_start<='0';ad_convst_start<='1';read_ad_state<="00001";elseread_ad_state<="0