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《eda技术与vhdl课后答案(第3版)潘松 黄继业》由会员上传分享，免费在线阅读，更多相关内容在教育资源-天天文库。
1、第3章VHDL基础习题3-1如图所示3-2程序：IF_THEN语句LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21SPORT(s1,s0:INSTD_LOGIC_VECTOR;a,b,c,d:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREoneOFmux21ISBEGINPROCESS(s0,s1,a,b,c,d)BEGINIFs1=’0’ANDs0=’0’THENy<=a;ELSIFs1=’0’ANDs0=’1’THENy<=b;ELSIFs1=’
2、1’ANDs0=’0’THENy<=c;ELSIFs1=’1’ANDs0=’1’THENy<=d;ELSEy<=NULL;ENDIF;ENDPROCESS;ENDARCHITECTUREone;CASE语句LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21ISPORT(s1,s0:INSTD_LOGIC_VECTOR;a,b,c,d:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREtwoOFmux21ISSIGNALs:STD_LOGIC_VECTOR(
3、1DOWNTO0);BEGINs<=s1&s0;PROCESS(s)BEGINCASEsISWHEN“00”=>y<=a;WHEN“01”=>y<=b;WHEN“10”=>y<=c;WHEN“11”=>y<=d;WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;ENDARCHITECTUREtwo;3-3程序：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUXKISPORT(s0,s1:INSTD_LOGIC;a1,a2,a3:INSTD_LOGIC;outy:OUTSTD_LOGIC);ENDE
4、NTITYMUXK;ARCHITECTUREdoubleOFMUXKISSIGNALtmp:STD_LOGIC;--内部连接线BEGINp_MUX21A_u1:PROCESS(u1_s,u1_a,u1_b,u1_y)SIGNALu1_s,u1_a,u1_b,u1_y:STD_LOGIC;BEGINIFu1_s=’0’THENu1_y<=u1_a;ELSIFu1_y<=u1_b;ELSEu1_y<=NULL;ENDIF;ENDPROCESSp_MUX21A_u1;p_MUX21A_u2:PROCESS(u2_s,u2_a,u2_b,u2_y)SIGNALu2_s,u
5、2_a,u2_b,u2_y:STD_LOGIC;BEGINIFu2_s=’0’THENu2_y<=u2_a;ELSIFu2_y<=u2_b;ELSEu2_y<=NULL;ENDIF;ENDPROCESSp_MUX21A_u2;u1_s<=s0;u1_a<=a2;u1_b<=a3;tmp<=u1_y;u2_s<=s1;u2_a<=a1;u2_b<=tmp;outy<=u2_y;ENDARCHITECTUREdouble;3-4程序：（1）1位半减器1位半减器的设计选用（2）图，两种表达方式：一、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.A
6、LL;ENTITYh_suberISPORT(x,y:INSTD_LOGIC;s_out,diff:OUTSTD_LOGIC);ENDENTITYh_suber;ARCHITECTUREfhd1OFh_suberISBEGINdiff<=xXORy;s_out<=(NOTa)ANDb;ENDARCHITECTUREfhd1;二、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_suberISPORT(x,y:INSTD_LOGIC;s_out,diff:OUTSTD_LOGIC);ENDENTITYh_suber;ARC
7、HITECTUREfhd1OFh_suberISSIGNALs:STD_LOGIC_VECTOR(1DOWNTO0);BEGINs<=x&y;PROCESS(s)BEGINCASEsISWHEN“00”=>s_out<=’0’;diff<=’0’;WHEN“01”=>s_out<=’1’;diff<=’1’;WHEN“10”=>s_out<=’0’;diff<=’1’;WHEN“11”=>s_out<=’0’;diff<=’0’;WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;ENDARCHITECTUREfhd1;或门逻辑描述：LIBRA
8、RYIEE
