数字系统设计复习new

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1、一请用VHDL语言设计一个矩阵式键盘译码电路，输入端口为（clk,ky[1..0],kx[2..0]）,输出端口为（yout[2..0],只要求将键值输出即可，不需要输出标志位，其中功能键和数字键统一编码，编码表如表1所示，键盘连线如图1所示。表1按键编码按键编码按键编码100120103011410051016110LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYZZJPYMI

2、SPORT(CLK:INSTD_LOGIC;Y:INSTD_LOGIC_VECTOR(1DOWNTO0);x:INSTD_LOGIC_VECTOR(2DOWNTO0);yout:OUTSTD_LOGIC_VECTOR(2DOWNTO0);ENDENTITYZZJPYM;ARCHITECTUREARTOFZZJPYMISSIGNALN:STD_LOGIC_VECTOR(2DOWNTO0);BEGINPROCESS(CLK)BEGINZ<=y&x;IFCLK'EVENTANDCLK='1'THENCASEZISWHEN"10011"=>N<

3、="0001";--1WHEN"10101"=>N<="0010";--2WHEN"10110"=>N<="0011";--3WHEN"01011"=>N<="0100";--4WHEN"01101"=>N<="0101";--5WHEN"01110"=>N<="0110";--6WHENOTHERS=>N<="1111";ENDCASE;ENDIF;yout<=N;ENDARCHITECTUREART;二用VHDL设计一个显示控制电路，将4个共阳数码管上显示“4321”数据，其外部电路的接线示意图如图2所示。该控制器输入端口为（clk

4、），输出端口为（com[3..0],seg[7..0]）。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYDISPLAYISPORT(CLK:INSTD_LOGIC;-COM:OUTSTD_LOGIC_VECTOR(3DOWNTO0);SEG:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYDISPLAY;ARCHITECTUREARTOFDISPLAYISSIGNALCNT:STD_LOGIC_VEC

5、TOR(1DOWNTO0);PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENIFCNT="11"THENCNT<="000";ELSECNT<=CNT+'1';ENDIF;ENDIF;ENDPROCESS;PROCESS(CNT)BEGINCASECNTISWHEN"00"=>SEG<="1代码";;COM<="0001";WHEN"01"=>SEG<="2代码";COM<="0010";WHEN"10"=>SEG<="3代码";COM<="0100";WHEN"11"=>SEG<="4代码";COM

6、<="1000";WHENOTHERS=>SEG<="00000000";COM<="0000";ENDCASE;ENDPROCESS;ENDARCHITECTUREART;三状态控制器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYADZHKZISPORT(CLK:INSTD_LOGIC;EOC:INSTD_LOGIC;ALE，START，OE，LOCK:OUTSTD_LOGIC）;ENDENTITYADZHKZ;ARCHITECT

7、UREARTOFADZHKZISTYPESTATESIS(ST0，ST1，ST2，ST3，ST4，ST5，ST6);SIGNALCURRENT_STATE，NEXT_STATE:STATES;SIGNALALE0，START0，OE0，LOCK0：STD_LOGIC;BEGINPROCESS(CURRENT_STAT)ISBEGINCASECURRENT_STATEISWHENST0=>ALE0<=0';START0<='0';OE0<='0';NEXT_STATE<=ST1;WHENST1=>ALE0<='1;START0<='0';

8、OE0<='0';NEXT_STATE<=ST2;WHENST2=>ALE0<='0';START0<='1;OE0<='0';NEXT_STATE<=ST3;WHENST3=>ALE0<='0';STAR