数字信号处理的fpga实现

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1、数字信号处理的FPGA实现学院：班级：小组成员：第一题：要求：用无符号DA（分布式）算法实现3个系数{2，3，1}的FIR滤波器。1、原理:系数c[n]为已知常数，x[n]为变量则重新分布求和次序则有：2、移位-加法器DA结构：3、三阶FIR滤波器，设系数位宽为3，值为c[0]=2，c[1]=3，c[2]=1，则实现f(c[n],xb[n])的LUT为：LUT查找表：则结果应为：4、代码清单：DAfilter（FIR滤波器）、LUT（查找表）、DAtest（testbench文件）（1）DAfilter（FIR滤波器）代码

2、：LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_arith.ALL;PACKAGEda_packageISCOMPONENTLUT----元件例化PORT(table_in:INSTD_LOGIC_VECTOR(2DOWNTO0);table_out:OUTINTEGERRANGE0TO6);ENDCOMPONENT;ENDda_package;LIBRARYwork;USEwork.da_package.ALL;-----使用包LIBRARYieee;U

3、SEieee.std_logic_1164.ALL;USEieee.std_logic_arith.ALL;ENTITYDAfilterISPORT(clk:INSTD_LOGIC;x_in0,x_in1,x_in2:INSTD_LOGIC_VECTOR(2DOWNTO0);y:OUTINTEGERRANGE0TO63);ENDDAfilter;ARCHITECTUREfpgaOFDAfilterISTYPESTATE_TYPEIS(s0,s1);SIGNALstate:STATE_TYPE;SIGNALx0,x1,x2,

4、table_in:STD_LOGIC_VECTOR(2DOWNTO0);SIGNALtable_out:INTEGERRANGE0TO7;BEGINtable_in(0)<=x0(0);table_in(1)<=x1(0);table_in(2)<=x2(0);PROCESSVARIABLEp:INTEGERRANGE0TO63;--temp.registerVARIABLEcount:INTEGERRANGE0TO3;--countsshiftsBEGINWAITUNTILclk='1';CASEstateISWHENs

5、0=>---初始化状态state<=s1;count:=0;p:=0;x0<=x_in0;x1<=x_in1;x2<=x_in2;WHENs1=>IFcount=3THEN---count=3结束滤波y<=p;state<=s0;ELSEp:=p/2+table_out*4;----最终p=x(0)*4/2/2+x(1)*4/2+x(2)*4;x0(0)<=x0(1);----向右移位x0(1)<=x0(2);x1(0)<=x1(1);x1(1)<=x1(2);x2(0)<=x2(1);x2(1)<=x2(2);count

6、:=count+1;state<=s1;ENDIF;ENDCASE;ENDPROCESS;LC_Table0:LUTPORTMAP(table_in=>table_in,table_out=>table_out);ENDfpga;（2）LUT（查找表）代码：LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_arith.ALL;ENTITYLUTISPORT(table_in:INSTD_LOGIC_VECTOR(2DOWNTO0);table_out:OUTI

7、NTEGERRANGE0TO6);ENDLUT;ARCHITECTURELEsOFLUTISBEGIN--ThisistheDACASEtablefor--the3coefficients:2,3,1--automaticallygeneratedwithdagen.exe--DONOTEDIT!PROCESS(table_in)BEGINCASEtable_inISWHEN"000"=>table_out<=0;WHEN"001"=>table_out<=2;WHEN"010"=>table_out<=3;WHEN"01

8、1"=>table_out<=5;WHEN"100"=>table_out<=1;WHEN"101"=>table_out<=3;WHEN"110"=>table_out<=4;WHEN"111"=>table_out<=6;WHENOTHERS=>table_out<=0;ENDCASE;ENDPRO