实验六 16×16led点阵

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1、实验六利用可编程逻辑器件进行一个16×16LED点阵控制接口的设计一、实验目的了解LED点阵显示的原理及接口驱动方法。二、实验任务利用VHDL语言进行点阵控制接口的设计在点阵上实现字符的分时显示三、点阵控制接口的设计在实验仪器中，16×16点阵显示的驱动电路已经做好，并且其行选通信号为一4-16译码器的输出，所以我们在设计点阵控制接口时，其行选通信号输出必须经4-16编码。系统框图如下：（1）分频模块libraryieee;Useieee.std_logic_1164.all;useieee.std_logic_unsigned

2、.all;entityfenpinisport(clk:instd_logic;clkout:outstd_logic);endfenpin;architecturechw_arcoffenpinissignalcnt:integerrange0to999;beginprocess(clk)beginifclk'eventandclk='1'thenifcnt<499thenclkout<='0';elseclkout<='1';endif;cnt<=cnt+1;endif;endprocess;endchw_arc;（2）CH

3、W模块此模块是用来控制每个字母的显示时间，改变常数可改变显示时间。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitychwisport(clk:instd_logic;q:outstd_logic_vector(1downto0));endchw;architecturechw_arcofchwisbeginprocess(clk)variablecnt:integer;Variabletmp:std_logic_vector(

4、1downto0);beginifclk'eventandclk='1'thenifcnt<10000thencnt:=cnt+1;elsecnt:=0;iftmp="11"thentmp:="00";elsetmp:=tmp+1;endif;endif;endif;q<=tmp;endprocess;endchw_arc;（3）CNTA模块此模块产生行选通信号。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycntaispo

5、rt(clk:instd_logic;q:outstd_logic_vector(3downto0));endcnta;architecturecnt_arcofcntaisbeginprocess(clk)variabletmp:std_logic_vector(3downto0);beginifclk'eventandclk='1'theniftmp="1111"thentmp:="0000";elsetmp:=tmp+1;endif;endif;q<=tmp-1;--总数减1的输出endprocess;endcnt_arc

6、;（4）CORA模块此模块对应产生列字符扫描信号libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycoraisport(ch:instd_logic_vector(1downto0);sel:instd_logic_vector(3downto0);q:outstd_logic_vector(15downto0));endcora;architecturecorn_arcofcoraisbeginprocess(ch,sel)b

7、egincasechiswhen"00"=>caseseliswhen"0000"=>q<="0110000000000000";when"0001"=>q<="0111100000000000";when"0010"=>q<="0001111000000000";when"0011"=>q<="0000011110000000";when"0100"=>q<="0000000111100000";when"0101"=>q<="0000000001111000";when"0110"=>q<="0000000000011110

8、";when"0111"=>q<="0000000000000111";when"1000"=>q<="0000000000000111";when"1001"=>q<="0000000000011110";when"1010"=>q<="00000000011