【精品】时序分析基础.doc

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1、Quartus®IISoftwareDesignSeries:TimingAnalysis・Timinganalysisbasics£>2009AJteeCorporation时序分析基础ObjectivesDisplayacompleteunderstandingoftiminganalysis目的：对时序分析有一个完整的认识Howdoestimingverificationwork?Everydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications

2、/requirements一Catchtiming-relatederrorsfasterandeasierthangate-levelsimulation&boardtestingDesignermustentertimingrequirements&exceptions-Usedtoguidefitterduringplacement&routing一Usedtocompareagainstactualresults©2009A*e«CoqxxattonUerA.Svatbc.Ante.Cyclone.MAX.HardC

3、ooy.Ntoa.QuatfiA.andMegaCocearevademaftaofAkeraCorporaion3如何核杳工作时间TimingAnalysisBasicsLaunchvs.latchedgesSetup&holdtimesData&clockarrivaltimeDatarequiredtimeSetup&holdslackanalysisI/OanalysisRecovery&removalTimingmodels时序分析基础锁存比较锁存沿设置和保持时间数据和时钟到达时间数据必须时间设置和保持slack分

4、析I/O分析恢复和消除时序模型Path&AnalysisTypesAsyncPathThreetypesofPaths:1.ClockPaths2.DataPathAsynchronousPaths*TwotypesofAnalysis:1.Synchronous-clock&datapaths2Asynchronous*-clock&asyncpathsAsynchronousreferstosignalsfeedingtheasynchronouscontrolportsoftheregisters©2009AteoCo

5、rporationSratta.5a.Cyclone.MAX.KaSCopy.Nbt.Wus.andl^egaCocearerademarkeofAteraCocpocatonLaunch&LatchEdgesCLKDATAXDataValidXLatchEdgeLaunchEdge:LatchEdge:theedgewhichJaunchesMthedatafromsourceregistertheedgewhich"latches0thedataatdestinationregister(withrespecttothe

6、launchedge,selectedbytiminganalyzer;typically1cycle)©2009AAeaCorporationAfcera,Svatk,Ama.Cyclone,MAX,HardCo(>y.NgQuaCub.andMegaCor©arevademartaofAlecaCorporaion6respectSetup&HoldDATAPRECLKDQTsu%CLKCLRDATAXValidXSetup:TheminimumtimedatasignalmustbestableBEFOREclocke

7、dgeHold:TheminimumtimedatasignalmustbestableAFTERclockedgeTogether,thesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.建立吋间:保持吋间:DataArrivalTimeThetimefordatatoarriveatdestinationregister'sDinputDataArrivalTime=launchedge+T

8、c(k1+Tco+Tdata©2009Alte