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1、1.1.分析下面程序，说出该程序的功能。Entitytestisgeneric(setup_time:time:=5ns);poil(D:instdjogic;Q:outsld」ogic;elk:instd_logic);endtest;architecturetestoftestisbeginprocess(clk)beginifclk=Tandclk^eventthenassert(D^last_event>setup_time)report“setupviolation^severityerror;endif;endtest;2.2.分析下面程序，说出该程序的功能。l
2、ibraryIEEE;useIEEE.STD_LOGIC_1164.all;entitys_machineisport(elk:inSTD_LOGIC;rst:inSTD_LOGIC;din:inSTE)1.LOGIC;coinb_output:outSTD_L0GIC)；ends_machine;architectures_machineofs_machineistypestatesis(stO,stl,st2,st3);signalcur_state,next_state:states;beginprocess(clk,rst)beginifrst='1'thencur
3、_state<=stO;elsifclk^ventandclk=Tthencur_state<=next_state;endif;endprocess;process(cur_state,next_state)begincasecur_stateiswhenst()=>comb_output<='0,;ifdin=415thennext_state<=stl;elsenext_state<=stO;endif;whenst1=>comb_output<=40,;ifdin=4rthennext_state<=sl2;elsenext_state<=stO;endif;whe
4、nst2=>ifdin二Tthennext_state<=st3;comb_output<=4r；elsenext_state<=stO;comb_output<='0^;endif;whenst3=>讦state_input=4l'thennext_state<=st3;comb_output<='r；elsenext_state<=stO;comb_output<='0,;endif;endcase;endprocess;ends_machine;1.3.分析下面程序，指出该程序的功能。process(a,dr,en)beginifen='O'anddr=*1'then
5、bout<=a;elsebout<=',ZZZZZZZZ,;endif;b<=bout;endprocess;process(a,dr,en)beginifen='O'anddr='O*thenaoul<=b;elseaout<="ZZZZZZZZH;endif;a<=aout;endprocess;2.4.分析下而程序，指出电路功能。libraryIEEE;uselEEE.STD_LOGlC_1164.all;entityshiftisport(clk:inSTD_LOGIC;a:inSTD_LOGIC;b:outSTD_L0GIC);endshift;architect
6、ureshiftofshiftisbegincomponentdffport(d,clk:ins(d」ogic;q:outstd_logic);endcomponent;signalz:std_logic_vector(0to4);beginz(0)<=a;gkforiin0to3generatedffx:dffportmap(z(i),clk,z(i+l));endgenerate;b<=z(4);endshift;5•分析下而程序，所明该程序的功能。libraryIEEE;useIEEE.STD_LOGIC_1164.all;entitychkisport(din:in
7、STD_L0GIC;clk,clr:inSTD_L0GIC;d:inSTD_L0GIC_VECT0R(7downto0);check_out:outSTD_LOGIC)；endchk;architecturechkofchkissignalq:integerrange0to8;beginprocess(clk,clr)beginifclr='Tthenq<=();elsifclk^ventandelk二Tthencaseqiswhen0=>ifdin=d(7)thenq<=l;elseq<=0;endif;when
