组合逻辑电路的设计和分析

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1、组合逻辑电路的设计和分析1概述2编码器3译码器4简单数字显示系统5其它定义：任一时刻的输出仅仅取决于当时的输入，与电路原来的状态无关，这样的数字电路叫做组合逻辑电路。常用组合逻辑电路有以下几种：（1）编码器（2）译码器（3）比较器（4）数据选择器（5）三态输出电路（6）加法器1概述2编码器2.18-3编码器2.2二－十进制编码器编码器有普通编码器和优先编码器，我们设计一个普通的8-3编码器。输入信号输出信号使能端口一、外观及功能2.18-3编码器注：EN为1时编码器工作二、其VHDL程序结构体1实体architecturem2ofbmqisbeginprocess(a)begi

2、nifen='1'thencaseaiswhen"00000001"=>Y<="000";when"00000010"=>Y<="001";when"00000100"=>Y<="010";when"00001000"=>Y<="011";when"00010000"=>Y<="100";when"00100000"=>Y<="101";when"01000000"=>Y<="110";when"10000000"=>Y<="111";whenothers=>y<="000";endcase;elsey<="000";endif;endprocess;endm2;结构体25.2

3、.2二－十进制编码器一、外观及功能二、其VHDL程序libraryieee;useieee.std_logic_1164.all;entitybmqisport(A:instd_logic_vector(9downto0);B:outstd_logic_vector(3downto0));endbmq;architecturem1ofbmqisbeginB<="0000"whenA="0000000001"else"0001"whenA="0000000010"else“0010"whenA="0000000100"else“0011"whenA="0000001000"els

4、e“0100"whenA="0000010000"else“0101"whenA="0000100000"else“0110"whenA="0001000000"else“0111"whenA=“0010000000"else“1000"whenA=“0100000000"else“1001"whenA=“1000000000"else“1111"endm1;结构体实体3译码器3.13-8译码器3.2七段显示码译码器3.13-8译码器一、外观及功能二、其VHDL程序libraryieee;useieee.std_logic_1164.all;entityymqisport(Y:

5、instd_logic_vector(2downto0);EN:instd_logic;A:outstd_logic_vector(7downto0));endymq;architecturem1ofymqisbeginprocess(y)beginifen='1'thencaseyiswhen"000"=>A<="00000001";when"001"=>A<="00000010";when"010"=>A<="00000100";when"011"=>A<="00001000";when"100"=>A<="00010000";when"101"=>A<="00100000

6、";when"110"=>A<="01000000";when"111"=>A<="10000000";whenothers=>A<="11111111";endcase;elseA<="11111111";Endif;endprocess;endm1;3.2七段显示码译码器一、外观及功能二、其VHDL程序Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityxianisPort(C:instd_logic_vector(3downto0);D:outstd_logic_vecto

7、r(6downto0));Endxian;Architecturea1ofxianisBeginD<="0111111"whenC="0000"else--0"0000110"whenC="0001"else--1"1011011"whenC="0010"else--2"1001111"whenC="0011"else--3"1100110"whenC="0100"else--4"1101101"whenC="0101"else--5"1111101"whenC="0110"else--6"