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《基于Verilog的汽车尾灯控制》由会员上传分享，免费在线阅读，更多相关内容在行业资料-天天文库。
1、代码顶层模块：modulecar_led(clk,rst,r,l,b,led_r,led_l);inputclk,rst,r,l,b;output[2:0]led_r,led_l;contralcontral(.clk_n(clk_n),.r(r),.l(l),.b(b),.led_r(led_r),.led_l(led_l));div_1hzdiv_1hz(.clk(clk),.rst(rst),.clk_n(clk_n));Endmodule计数分频：modulediv_1hz(clk,rst,clk_n);inputclk,rst;outputclk_n;reg[31:0]cin
2、;regclk_n;always@(posedgeclkornegedgerst)beginif(!rst)begincin=0;endelseif(cin<24999999)cin=cin+1'b1;elsecin=0;endalways@(posedgeclk)beginif(cin<=12499999)clk_n<=1;elseclk_n<=0;endendmodule灯控制模块：modulecontral(clk_n,r,l,b,led_r,led_l);inputclk_n,r,l,b;output[2:0]led_r,led_l;reg[2:0]led_r,led_l;re
3、g[1:0]state;regi;always@(posedgeclk_n)beginif(state<2)state<=state+1;elsestate<=0;endalways@(posedgeclk_n)begini<=~i;endalways@(posedgeclk_n)beginif(b==0)begincase(i)0:beginled_r<=3'b001;led_l<=3'b000;end1:beginled_r<=3'b110;led_l<=3'b111;endendcaseendelseif(r==1&&l==0)begincase(state)0:beginled
4、_r<=3'b001;led_l<=3'b100;end1:beginled_r<=3'b001;led_l<=3'b010;end2:beginled_r<=3'b001;led_l<=3'b001;enddefault:beginled_r<=3'b001;led_l<=3'b100;endendcaseendelseif(r==0&&l==1)begincase(state)0:beginled_r<=3'b101;led_l<=3'b000;end1:beginled_r<=3'b011;led_l<=3'b000;end2:beginled_r<=3'b000;led_l<=
5、3'b000;enddefault:beginled_r<=3'b101;led_l<=3'b000;endendcaseendelsebeginled_r<=3'b001;led_l<=3'b000;endendendmodule
