CHAPTER 4 The Components of the System 2. Processor 课件

《CHAPTER 4 The Components of the System 2. Processor 课件》由会员上传分享，免费在线阅读，更多相关内容在教育资源-天天文库。

CHAPTER4TheComponentsoftheSystemUnitProcessor FundamentalConceptsProcessorfetchesoneinstructionatatimeandperformtheoperationspecified.Instructionsarefetchedfromsuccessivememorylocationsuntilabranchorajumpinstructionisencountered.ProcessorkeepstrackoftheaddressofthememorylocationcontainingthenextinstructiontobefetchedusingProgramCounter(PC).InstructionRegister(IR) ExecutinganInstructionFetchthecontentsofthememorylocationpointedtobythePC.ThecontentsofthislocationareloadedintotheIR(fetchphase).IR←[[PC]]Assumingthatthememoryisbyteaddressable,incrementthecontentsofthePCby4(fetchphase).PC←[PC]+4CarryouttheactionsspecifiedbytheinstructionintheIR(executionphase). InternalorganizationoftheprocessorALURegistersfortemporarystorageVariousdigitalcircuitsforexecutingdifferentmicrooperations.(gates,MUX,decoders,counters).InternalpathformovementofdatabetweenALUandregisters.Drivercircuitsfortransmittingsignalstoexternalunits.Receivercircuitsforincomingsignalsfromexternalunits. PC:KeepstrackofexecutionofaprogramContainsthememoryaddressofthenextinstructiontobefetchedandexecuted.MAR:Holdstheaddressofthelocationtobeaccessed.I/PofMARisconnectedtoInternalbusandanO/ptoexternalbus.MDR:Containsdatatobewrittenintoorreadoutoftheaddressedlocation.IThas2inputsand2Outputs.DatacanbeloadedintoMDReitherfrommemorybusorfrominternalprocessorbus.ThedataandaddresslinesareconnectedtotheinternalbusviaMDRandMAR ALU:Usedtoperformarithmeticandlogicaloperation.DataPath:Theregisters,ALUandinterconnectingbusarecollectivelyreferredtoasthedatapath. Registers:TheprocessorregistersR0toRn-1varyconsiderablyfromoneprocessortoanother.Registersareprovidedforgeneralpurposeusedbyprogrammer.Specialpurposeregisters-index&stackregisters.RegistersY,Z&TEMParetemporaryregistersusedbyprocessorduringtheexecutionofsomeinstruction.Multiplexer:SelecteithertheoutputoftheregisterYoraconstantvalue4tobeprovidedasinputAoftheALU.Constant4isusedbytheprocessortoincrementthecontentsofPC. Datatransferbetweentworegisters:EX:TransferthecontentsofR1toR4.EnableoutputofregisterR1bysettingR1out=1.ThisplacesthecontentsofR1ontheprocessorbus.EnableinputofregisterR4bysettingR4in=1.ThisloadsthedatafromtheprocessorbusintoregisterR4. TheinputandoutputgatesforregisterRiarecontrolledbysignalsisRinandRiout.RinIssetto1–dataavailableoncommonbusareloadedintoRi.RioutIssetto1–thecontentsofregisterareplacedonthebus.RioutIssetto0–thebuscanbeusedfortransferringdatafromotherregisters. Datatransferbetweentworegisters:EX:TransferthecontentsofR1toR4.EnableoutputofregisterR1bysettingR1out=1.ThisplacesthecontentsofR1ontheprocessorbus.EnableinputofregisterR4bysettingR4in=1.ThisloadsthedatafromtheprocessorbusintoregisterR4. PerforminganArithmeticorLogicOperationTheALUisacombinationalcircuitthathasnointernalstorage.ALUgetsthetwooperandsfromMUXandbus.TheresultistemporarilystoredinregisterZ.WhatisthesequenceofoperationstoaddthecontentsofregisterR1tothoseofR2andstoretheresultinR3?R1out,YinR2out,SelectY,Add,ZinZout,R3in Step1:OutputoftheregisterR1andinputoftheregisterYareenabled,causingthecontentsofR1tobetransferredtoY.Step2:Themultiplexer’sselectsignalissettoselectYcausingthemultiplexertogatethecontentsofregisterYtoinputAoftheALU.Step3:ThecontentsofZaretransferredtothedestinationregisterR3. FetchingaWordfromMemoryTheresponsetimeofeachmemoryaccessvaries(cachemiss,memory-mappedI/O,…).Toaccommodatethis,theprocessorwaitsuntilitreceivesanindicationthattherequestedoperationhasbeencompleted(Memory-Function-Completed,MFC).Move(R1),R2MAR←[R1]StartaReadoperationonthememorybusWaitfortheMFCresponsefromthememoryLoadMDRfromthememorybusR2←[MDR] storingawordinmemoryAddressisloadedintoMARDatatobewrittenloadedintoMDR.Writecommandisissued.Example:MoveR2,(R1)R1out,MARinR2out,MDRin,WriteMDRoutE,WMFC ExecutionofaCompleteInstructionAdd(R3),R1FetchtheinstructionFetchthefirstoperand(thecontentsofthememorylocationpointedtobyR3)PerformtheadditionLoadtheresultintoR1