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Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012英文

Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012英文

ID：39578236

大小：1.03 MB

页数：13页

时间：2019-07-06

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1、DesignPatternsbyExampleforSystemVerilogVerificationEnvironmentsEnabledbySystemVerilog1800-2012EldonNelsonM.S.P.E.IntelCorporation(eldon_nelson@ieee.org)Abstract-“DesignPatterns”,publishedin1994,iswidelyseenaspopularizingtheideaofsoftwaredesignpatterns.Thebookcontainedexplanationsandapplication

2、sofsoftwaredesignpatternsandgavethemtheirdefinitivenames.Themiss-ingcomponenttoactualimplementationofmanyofthedesignpatternsinSystemVerilogislanguagesupport,whichhasonlyrecentlybecomeavailablewiththereleaseoftheSystemVerilog1800-2012specification.Thispaperwillrealizedesignpatternexamplesfromth

3、ebook“HeadFirstDesignPatterns”—originallywritteninJava—andportthemtoSystemVeri-logwhilebeingastruetotheoriginalimplementationaspossible.ThegoalwillbetoexposethatmanydesignpatternsarenowpossibletoimplementinSystemVerilog1800-2012.Applicationsofthosedesignpatternstailoredtoverificationenvi-ronme

4、ntsisdemonstratedtoshowitsusefulness.I.INTRODUCTIONModernverificationenvironmentscreatedinaframeworksuchasUVMencapsulatelessonslearnedfromyearsofsoftwaredesignexperimentationbythecomputersciencecommunity.However,therearecornerstonesofsoftwaredesignthatarenotwidelydeployedinUVMverificationenvir

5、onments.Thesemissingsoftwaredesignlessonsmakeithardertocreateflexibleverificationenvironmentscapableofmeetingcurrentverificationneeds.Thebook“DesignPatterns”[1]publishedin1994iswidelyseenaspopularizingtheideaofsoftwaredesignpat-terns.Thebookcontainedexplanationsandapplicationsofsoftwaredesignp

6、atternsandgavethemtheirdefinitivenames.UVMborrowsfrom“DesignPatterns”forsomeaspectsofitsdesign.Forexample,theUVMFactorycon-formstomanyoftheideasoftheFactoryPatterndescribedin“DesignPatterns”.Themissingcomponenttoactualimplementationofmanyofthedesignpatternsislanguagesupport,whichhasonlyrecentl

7、ybecomeavailablewiththereleaseoftheSystemVerilog1800-2012specification[2].Withoutlanguagesupport,manyofthedesignpatternsaredifficulttorecognizeorareimpossibletoimplementproperly.Forexample,theSystemVerilogconstruct“implements”(Figure1)i

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