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1、时钟发生器：moduleclk_gen(clk,reset,clk1,fetch,alu_clk);inputclk,reset;outputclk1,fetch,alu_clk;wireclk,reset;regfetch,alu_clk;reg[7:0]state;parameterS1=8'b00000001,S2=8'b00000010,S3=8'b00000100,S4=8'b00001000,S5=8'b00010000,S6=8'b00100000,S7=8'b01000000,S8=8
2、'b10000000,idle=8'b00000000;assignclk1=~clk;always@(negedgeclk)if(reset)beginfetch<=0;alu_clk<=0;state<=idle;endelsebegincase(state)S1:beginalu_clk<=1;state<=S2;endS2:beginalu_clk<=0;state<=S3;endS3:beginfetch<=1;state<=S4;endS4:beginstate<=S5;endS5:sta
3、te<=S6;S6:state<=S7;S7:beginfetch<=0;state<=S8;endS8:beginstate<=S1;endidle:state<=S1;default:state<=idle;endcaseendendmodule指令寄存器：moduleregister(opc_iraddr,data,ena,clk,rst);output[15:0]opc_iraddr;input[7:0]data;inputena,clk,rst;reg[15:0]opc_iraddr;reg
4、state;always@(posedgeclk)beginif(rst)beginopc_iraddr<=16'b0000_0000_0000_0000;state<=1'b0;endelsebeginif(ena)begincasex(state)1'b0:beginopc_iraddr[15:8]<=data;state<=1;end1'b1:beginopc_iraddr[7:0]<=data;state<=0;enddefault:beginopc_iraddr[15:0]<=16'bxxx
5、xxxxxxxxxxxxx;state<=1'bx;endendcaseendelsestate<=1'b0;endendendmodule累加器：moduleaccum(accum,data,ena,clk1,rst);output[7:0]accum;input[7:0]data;inputena,clk1,rst;reg[7:0]accum;always@(posedgeclk1)beginif(rst)accum<=8'b0000_0000;elseif(ena)accum<=data;end
6、endmoduleALU算术运算器：modulealu(alu_out,zero,data,accum,alu_clk,opcode);output[7:0]alu_out;outputzero;input[7:0]data,accum;input[2:0]opcode;inputalu_clk;reg[7:0]alu_out;parameterHLT=3'b000,SKZ=3'b001,ADD=3'b010,ANDD=3'b011,XORR=3'b100,LDA=3'b101,STO=3'b110,
7、JMP=3'b111;assignzero=!accum;always@(posedgealu_clk)if(alu_clk)begincasex(opcode)HLT:alu_out<=accum;//暂停SKZ:alu_out<=accum;//ADD:alu_out<=data+accum;ANDD:alu_out<=data&accum;XORR:alu_out<=data^accum;LDA:alu_out<=data;STO:alu_out<=accum;JMP:alu_out<=accu
8、m;default:alu_out<=8'bxxxx_xxxxx;endcaseendendmodule数据控制器：moduledatactl(data,in,data_ena);output[7:0]data;input[7:0]in;inputdata_ena;assigndata=(data_ena)?In:8'bzzzz_zzzz;endmodule地址多路器：moduleadr(addr,fetch,ir_addr,pc_addr);outpu
