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1、PCI接口时序测试方法1.参考文献:(1)Intel(R)I/OControllerHub4(ICH4)ExternalDesignSpecification(EDS).(No.589)(2)PCISPECIFICATIONV2.2.2.测试目的:在P4D项目(Springdale-G/PE)中,主要看PCI接口的PCICLK,AD和C/BE#[3,0]等控制信号的时序质量是否满足规范要求.3.测试内容和规范特别说明:时序测试中PCI接口的参考电平的值为Vtest=-1.5v(对5V环境的PCI卡):ThefollowingisrefertoICH4.Table
2、19-10.PCIInterfaceTimingSymParameterMinMaxUnitsNotesFiguret40AD[31;0]ValidDelay211nsMin:0pFMax:50pF19-3t41AD[31:0]SetupTimetoPCICLKRising7ns19-4t42AD[31:0]HoldTimefromPCICLKRising0ns19-4t43C/BE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,PAR,PERR#,PLOCK#DEVSEL#ValidDelayfromPCICLKRising,211nsMin:
3、0pFMax:50pF19-3t44C/BE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,PAR,PERR#,PLOCK#IDSEL,DEVSEL#OutputEnableDelayfromPCICLKRising,2ns19-7t45C/BE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,PERR#,PLOCK#DEVSEL#,GNT[A:B]#FloatDelayfromPCICLKRising,228ns19-5t46C/BE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,SERR#,PERR#,DEVSE
4、L#,SetupTimetoPCICLKRising,7ns19-4t47C/BE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,SERR#,PERR#DEVSEL#,REQ[A:B]#HoldTimefromPCICLKRising,0ns19-4t48PCIRST#LowPulseWidth1ms19-6t49GNT[A:B]#,GNT[5:0]#ValidDelayfromPCICLKRising212nst50REQ[A:B]#,REQ[5:0]#SetupTimertoPCICLKRising12nsThefollowingisrefe
5、rtoPCIspec2.2.7.6.4.2TimingParametersTable7-4:66MHzand33MHzTimingParameters66MHz33MHz7SymbolParameterMinMaxMinMaxUnitsNotesTvalCLKtoSignalValidDelay-busedsignals26211ns1,2,3,8,Tval(ptp)CLKtoSignalValidDelay-pointtopointsignals26212ns1,2,3,8TonFloattoActiveDelay22ns1,8,9ToffActivetoFl
6、oatDelay1428ns1,9,TsuInputSetupTimetoCLK-busedsignals37ns3,4,10Tsu(ptp)InputSetupTimetoCLK-pointtopointsignals510,12ns3,4ThInputHoldTimeformCLK00ns4TrstResetActiveTimeafterpowerstable11ms5Trst-clkResetActiveTimeafterCLKstable100100us5Trst-offResetActivetooutputfloatdelay4040ns5,6trrs
7、uREQ64#toRST#setuptime10Tcyc10TcycnsTrrhRST#toREQ64#holdtime050050nsTrhfaRST#hightofirstConfigurationaccess225225ClocksTrhffRST#hightofirstFRAME#assertion55clocksNOTES:1.SeethetimingmeasurementconditionsinFigure7-3.ItisimportantthatalldrivensignaltransitionsdrivetotheirVohofVollevelw
8、ithinoneTcyc