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1、SynthesisandIntroductionSimulationUnderstandingHigh-DensityDesignFlowDesignGuideGeneralHDLCodingStylesArchitectureSpecificHDLCodingStylesforXC4000XLA,Spartan,andSpartan-XLArchitectureSpecificHDLCodingStylesforSpartan-II,Virtex,Virtex-E,andVirtex-IISimulatingYourDesignSynthesisandSimulationDesignG
2、uide—3.3.06iPrintedinU.S.A.SynthesisandSimulationDesignGuideSynthesisandSimulationDesignGuideRTheXilinxlogoshownaboveisaregisteredtrademarkofXilinx,Inc.ASYL,FPGAArchitect,FPGAFoundry,NeoCAD,NeoCADEPIC,NeoCADPRISM,NeoROUTE,TimingWizard,TRACE,XACT,XILINX,XC2064,XC3090,XC4005,XC5210,andXC-DS501arere
3、gisteredtrademarksofXilinx,Inc.TheshadowXshownaboveisatrademarkofXilinx,Inc.AllXC-prefixproductdesignations,A.K.ASpeed,AllianceSeries,AllianceCORE,BITA,CLC,ConfigurableLogicCell,CoolRunner,COREGenerator,CoreLINX,DualBlock,EZTag,FastCLK,FastCONNECT,FastFLASH,FastMap,FastZeroPower,Foundation,HardWi
4、re,IRL,LCA,LogiBLOX,LogicCell,LogiCORE,LogicProfessor,MicroVia,MultiLINX,PLUSASM,PowerGuide,PowerMaze,QPro,RealPCI,RealPCI64/66,SelectI/O,SelectRAM,SelectRAM+,SiliconXpresso,Smartguide,Smart-IP,SmartSearch,Smartspec,SMARTSwitch,Spartan,TrueMap,UIM,VectorMaze,VersaBlock,VersaRing,Virtex,WebFitter,
5、WebLINX,WebPACK,XABEL,XACTstep,XACTstepAdvanced,XACTstepFoundry,XACT-Floorplanner,XACT-Performance,XAM,XAPP,X-BLOX,X-BLOXplus,XChecker,XDM,XDS,XEPLD,XilinxFoundationSeries,XPP,XSI,andZERO+aretrademarksofXilinx,Inc.TheProgrammableLogicCompanyandTheProgrammableGateArrayCompanyareservicemarksofXilin
6、x,Inc.Allothertrademarksarethepropertyoftheirrespectiveowners.Xilinx,Inc.doesnotassumeanyliabilityarisingoutoftheapplicationoruseofanyproductdescribedorshownherein;nordoesitconveyanylicenseunderitspatents,copyrights,ormaskworkrightsoranyrightsofothers.Xilinx,Inc.reservestherighttomakechanges,atan
7、ytime,inordertoimprovereliability,functionordesignandtosupplythebestproductpossible.Xilinx,Inc.willnotassumeresponsibilityfortheuseofanycircuitrydescribedhereinotherthancircuitryentirelyembodiedinitsproducts.Xilinx,Inc