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1、TheMSP430x14x(1)hasasecondhardwareuniversalsynchronous/asynchronousreceivetransmit(USART1)peripheralmodulethatisusedforserialdatacommunication.TheUSARTsupportssynchronousSPI(3or4pin)andasynchronousUARTcommunicationprotocols,usingdouble-bufferedtransmitandreceivechannels.Operati
2、onofUSART1isidenticaltoUSART0TheclocksystemintheMSP430x13xandMSP43x14x(1)familyofdevicesissupportedbythebasicclockmodulethatincludessupportfora32768-Hzwatchcrystaloscillator,aninternaldigitally-controlledoscillator(DCO)andahighfrequencycrystaloscillator.Thebasicclockmoduleisdes
3、ignedtomeettherequirementsofbothlowsystemcostandlow-powerconsumption.TheinternalDCOprovidesafastturn-onclocksourceandstabilizesinlessthan6µs.Thebasicclockmoduleprovidesthefollowingclocksignals:1，Auxiliaryclock(ACLK),sourcedfroma32768-Hzwatchcrystalorahighfrequencycrystal.,2，Mai
4、nclock(MCLK),thesystemclockusedbytheCPU.3，Sub-Mainclock(SMCLK),thesub-systemclockusedbytheperipheralmodules.Theprimaryfunctionofthewatchdogtimer(WDT)moduleistoperformacontrolledsystemrestartafterasoftwareproblemoccurs.Iftheselectedtimeintervalexpires,asystemresetisgenerated.Ift
5、hewatchdogfunctionisnotneededinanapplication,themodulecanbeconfiguredasanintervaltimerandcangenerateinterruptsatselectedtimeintervals.hardwaremultiplier(MSP430x14xandMSP430x14x1Only)Themultiplicationoperationissupportedbyadedicatedperipheralmodule.Themoduleperforms1616,168,816,
6、and88bitoperations.Themoduleiscapableofsupportingsignedandunsignedmultiplicationaswellassignedandunsignedmultiplyandaccumulateoperations.Theresultofanoperationcanbeaccessedimmediatelyaftertheoperandshavebeenloadedintotheperipheralregisters.Noadditionalclockcyclesarerequired.osc
7、illatorandsystemclockUSART0Voidmain()While(){P1OUT^=BIT0;_delay_cycles(100000);}WDTCTL=WDTPW+WDTHOLD; BCSCTL1
8、=XT2OFF;BCSCTL3
9、=LFXT1S_2;//BCSCTL3
10、=LFXT1S_0;IE1&=~OFIE;IFG1&=~OFIFG;BCSCTL2
11、=SELM_3+SELS;//BCSCTL2
12、=SELM_0+SELS；__delay_cycles(1000);P1DIR=BIT0;P1OUT=BIT0;在MSP4
13、30单片机中一共有四个时钟源：（1）LFXT1CLK，为低速/高速晶振源，通常接32.768kHz晶振（2）
