集成电路课件

《集成电路课件》由会员上传分享，免费在线阅读，更多相关内容在行业资料-天天文库。

集成电路分析与设计第1讲认识集成电路设计及其设计过程2023/4/241 《集成电路分析与设计》课程主要介绍什么内容?CMOS数字集成电路(CMOSdigitalIC)IC的发展历史及现状(HistoryofIC)IC设计流程和方法(DesignprocessandMethodology)IC制造工艺技术(Fabricationprocess)ICEDA（CAD）工具使用(EDAtools)CMOS反相器设计(CMOSInverter)CMOS组合逻辑门设计(CombinationalLogicCircuit)CMOS时序逻辑电路设计(SequentialLogicCircuit)IC版图设计(Layout)IC仿真技术(Simulation)存储器电路设计介绍(MemoryCircuits)模拟IC设计介绍(AnalogIC)2023/4/242 《集成电路分析与设计》课程信息课程性质：是一门专业基础课程主要介绍CMOS数字集成电路设计的基础知识共40课时（32理论课时+8实验课时）完成4个实验对准备从事IC行业的学生来讲，本课程只是一个基础，还需要继续深入学习更多关于IC设计的知识，如数字IC深入，模拟IC，RFIC等。2023/4/243 实验内容（共8学时）实验一（2学时）反相器电路设计（SimulationandLayout）实验二（2学时）NAND电路设计（SimulationandLayout）实验三（2学时）AND电路设计（SimulationandLayout）实验四（2学时）D触发器电路设计（SimulationandLayout）2023/4/244 Project（选作内容）完成一个44SRAM芯片的设计3人一组项目过程：A期中OralpresentationB期末OralpresentationC项目报告书一份D3人项目成绩相同2023/4/245 GradingPolicy课堂提问和作业10%实验20%考试（开卷）70%规则：（1）1个问题和4次作业，每次/个2分，共10分；（2）每个实验完成得5分，共20分；（3）点名1次不到，10分没了；（4）抄作业，抄实验报告，相应分数没了；（5）请假规则：必须有正规请假手续和课前请假。2023/4/246 本课程推荐书目教材中文版周润德等译，数字集成电路设计透视第二版，电子工业出版社(JanM.Rabaey,etal.DigitalIntegratedCircuits,2nde,PrenticeHall,2004)参考书Sung-Mo(Steve)Kang,YusufLeblebici,CMOSDigitalIntegratedCircuitsAnalysis&Design,3rdEdition,McGraw-Hill2003R.JacobBaker,CMOSCircuitDesign,Layout,andsimulation,3rdEdition,Wiley,2010韩雁，集成电路设计CAD/EDA工具实用教程，机械工业出版社，20102023/4/247 IC设计优秀书目推荐模拟集成电路Razavi，模拟CMOS集成电路设计，清华大学出版社，2005通用参考书（Bible）威斯特，CMOS超大规模集成电路设计，第三版，中国电力出版社2023/4/248 几个常见缩略词CMOS(complementarymetaloxidesemiconductor)IC(integratedcircuit)VLSI(verylargescaleintegrated)ULSI(ultra-largescaleintegrated)MOSFET(metaloxidesemiconductorfieldeffecttransistors)SPICE(simulationprogramwithintegratedcircuitemphasis)2023/4/249 认识集成电路和集成电路设计为什么需要集成电路？与以前的集成电路设计相比，为什么现在的集成电路设计出现了不同以及现在的集成电路设计遇到了哪些新的挑战？未来，集成电路将如何发展？2023/4/2410 为什么需要集成电路?Integrationreducesdevicesize（减小尺寸）Laptop,iPod,mp3,cellphone,...Integrationimprovesthedesign（提高性能）higherspeed;lowerpowerconsuption;morereliable.Integrationreducesmanufacturingcost（降低成本）BOM(BoardofMaterials)costreducesMassICproductionreducescost2023/4/2411 ElectronicsIndustryDesign,fab,applicationEducationSoftwareCommunication/NetworkingFabcost:$2-$3billionDrivingforceofworldeconomyLargeinvestment:fab,packaging,design,EDAPentium®4“Northwood”55Mtransistors/2-2.5GHzL=0.13µm2023/4/2412 Moore’sLaw(1965)GordonMoore–IntelFounder“Thenumberoftransistorsonachipdoubledevery18to24months.”Electronics,April19,1965.GordonMooreIntelCo-FounderandChairmainEmeritusImagesource:IntelCorporationwww.intel.com2023/4/2413 InformationRevolutionElectronicsystemincars.Electronicfinancialsystem:e-banking,e-money,e-stock,RFIDlablePersonalcomputing/entertainmentMedicalelectronicsystems.Internet:routers,firewalls,servers,storagesElectroniclibrary(Google,...)DVDR/W,HDTV,InteractiveTVIngeneral,consumerelectronicsetc...2023/4/2414 ChallengesofICDesignComplexity:Multi-milliontransistorsonasinglechip(smallersize/fasterspeed)Multipleandconflictingspecificationsforhighperformance(power/speed/throughput)Competition:ShortdesigntimeDesignTools:Multipletoolsinvolved,ComplexdesignflowAnalogBasebandDigitalBaseband(DSP+MCU)PowerManagementSmallSignalRFPowerRF2023/4/2415 RelatedtoICJobs�Layoutdesigners�Circuitdesigners(Digital/Analog/RF)�Architects�Test/Verificationengineers�Fabricationengineers�Systemdesigners(SoC)�CADtoolprogrammersEmbeddedSystemdevelopersSoftwareprogrammers2023/4/2416 2023/4/2417 TheTransistorRevolutionFirsttransistorBellLabs,1947J.Bardeen,W.Shockley,andW.Brattain(1956NobelprizeLaureate)2023/4/2418 1958年J.Kilby（TI）研制成功第一个集成电路1959年R.Noyce（Fairchild）第一个利用平面工艺制成集成电路TheFirstIntegratedCircuits2023/4/2419 TheFirstIntegratedCircuitsBipolarlogic1960’sECL3-inputGateMotorola1966FirstcommercialIClogicgates–Fairchild1960TTL–1962intothe1990’sECL–1974intothe1980’s2023/4/2420 Intel4004Micro-Processor19702300transistors~1MHzoperation2023/4/2421 IntelPentium(IV)microprocessorPentium®4“Northwood”CommercialProduction:Year2001L=0.13µm6MLCuLow-kFC-PGA22023/4/2422 MOSFETTechnologyMOSFETtransistor-Lilienfeld(Canada)in1925andHeil(England)in1935CMOS–1960’s,butplaguedwithmanufacturingproblems(usedinwatchesduetotheirpowerlimitations)PMOSin1960’s(calculators)NMOSin1970’s(4004,8080)–forspeedCMOSin1980’s–preferredMOSFETtechnologybecauseofpowerbenefitsBiCMOS,Gallium-Arsenide,Silicon-GermaniumSOI,Copper-LowK,strainedsilicon,High-kgateoxide...2023/4/2423 WorldwideSemiconductorRevenueSource:ISSCC2003G.Moore“Noexponentialisforever,but‘forever’canbedelayed”2023/4/2424 1’’Waferin1964vs.300mm(12”)Waferin20032023/4/2425 IBMPowerPC970(130nm)20031.8Ghz58M118mm2ApplePowerG5,thefastestPCin2003,hasdualPPC970CPU2023/4/2426 TwochipsyouareseeingtodayMicroprocessorASIC(ApplicationSpecificIC)2023/4/2427 State-of-theArt:LeadMicroprocessors2023/4/2428 State-of-theArt:LeadMicroprocessors(uptodate)Pentium4180nm(2001)1.7GHz42Mtransistors217mm2Pentium4130nm(2003)3.2GHz55MTransistors131mm2Pentium490nm(2004)3.4Hz125MTransistors112mm2Pentiumon65nm(2005/2006)250MillionPentiumon45nm(2007)400to500MillionFreq(HZ)TransistorsDiesizemm2PowerDateServerIBMPower4+1.7G180M267N/A2003Itanium21.5G410M374130W2003IBMPower52G276M389N/A2004/2PCIBMPowerPC9701.8G58M11842W2003/6Pentium43.2G55M13182W2003/6AMDAthlon642.2G105M19289W2003/9Pentium4(Prescott)3.4G125M112103W2004/2(Alluse0.13umtechnologyexceptPentium4–Prescott,whichuses90nmtech)2023/4/2429 State-of-theArt:LeadMicroprocessors(uptodate)300mmwaferandPentium4IC.PhotoscourtesyofIntel.2023/4/2430 WhatADigitalDesignerNeedstoKnow...“MicroscopicProblems”•Ultra-highspeeddesignInterconnect•Noise,Crosstalk•Reliability,Manufacturability•PowerDissipation•Clockdistribution.“MacroscopicIssues”•Time-to-Market•MillionsofGates•High-LevelAbstractions•Reuse&IPAvailability•systemsonachip(SoC)•Predictability•etc.2023/4/2431 2023/4/2432 2023/4/2433 2023/4/2434 2023/4/2435 2023/4/2436 2023/4/2437 2023/4/2438 >95%2023/4/2439 如何设计一个集成电路？2023/4/2440 2023/4/2441 TheVLSIdesignprocess工程的艺术Maybepartoflargerproductdesign.Majorlevelsofabstraction:specificationarchitecturelogicdesigncircuitdesignlayoutdesign2023/4/2442 MajorSegmentsofICIndustryFablessDesignHousesEDAToolsCompaniesDesignServiceCompaniesLibrary&IPProvidersDedicatedICManufacturers(Foundry)Post:EDA:ElectronicDesignAutomationIP:siliconIntellectualPropertyIDM:IntegratedDeviceManufacturerIntegratedservicePackaging&TestingHouses2023/4/2443 ASICDesignStylesFullCustomDesignFlowCircuitiscreatedbycomposingatransistornetlistSPICEsimulationisperformedtoverifythecircuitKnownas“capture-and-simulate”paradigmLayoutismostlydonemanuallyPopularforhigh-performancemicroprocessors&memoriesCell-BasedSynthesisFlowDesignisfirstdescribedbyHardwareDescriptionLanguage(e.g.,VerilogandVHDL)Basedonacelllibrary,netlistiscreatedbysynthesistoolsKnownas“describe-and-synthesize”paradigmLayoutcanbedonethroughautomatictools2023/4/2444 DetailedCustomDesignFlowBlockSpecification(FiniteStateMachine,ArithmeticExpression,BooleanExpression)LogicDesignGate-LevelNetlistTransistorNetlistTechnologyMappingSPICESimulationSPICEModelLayoutDesignLayoutLayoutRulesDesignRuleChecking(DRC)Layoutvs.SchematicCheck(LVS)Parasitic(orwiring)RCextractionPost-LayoutSPICESimulationCheckifSPECismet?Ifyes,done.Otherwise,gobacktooptimizethedesign2023/4/2445 ASimpleExampleFunctionalityOne-bitbinaryfull-adderTechnology1mmn-wellCMOStechnologySpeedInputtooutputdelay<5nsArea<3000mm2PowerDissipation<1mWat5voltsand200MHzFull-adderABSumCarry_outSum=A⊕B⊕C=ABC+ABC+ABC+ACBCarry_out=AB+BC+CA(majorityfunction)BooleanDescriptionC2023/4/2446 LogicDesignLogicminimizationtrick:Thecarry_outsignalisusedtorealizethefunctionofsignalsuminordertoreducetheoverallcircuitsize.Today’slogicsynthesistools(suchasDesignCompiler)incorporatingsomeadvancedalgorithms,isabletoperformautomaticlogicminimization.x=Carry_out#of‘1’sInA,B,CCarry_outSum012300110101(A+B+C)x=>exactlyoneofA,B,Cis‘1’2023/4/2447 Transistor-LevelSchematicTechnologymappingManysimpleANDORgatesaremergedintoacomplexgate(oracellinthecelllibrary)TransistoraspectratiopMOS(W/L)isusuallylargerthannMOS(W/L),e.g.,2:1xyxyx=(AB+BC+CA)y=(A+B+C)x+ABC)2023/4/2448 InitialLayoutPost-layoutSPICEsimulationincludesthe“parasiticresistance&capacitance”ismoreaccuratethanthepre-layoutsimulation(pre-sim)Ratioofchannelwidths2:12023/4/2449 I/OSimulationWaveformsPropagationtimetPHLortPLHasdefinedaboveLow-to-highpropagationtime（传播延时）tPLH=8.2ns!Gottogobacktooptimizethedesign!!!C(Carry_in)Sum2023/4/2450 OptimizedLayoutTransistorSizingchangestheaspectratios(W/L)ofselectedtransistorsAlargeraspectratiomayleadtoahigherspeedWireSizingisalsomorerecentlyproposedPropagationDelay<5ns!2023/4/2451 FullCustomDesignExample（another)A/DPLAI/OcompRAMMetal1ViaMetal2I/OPadRandomlogic(standardcelldesign)2023/4/2452 Cell-BasedDesignFlowArchitecturedesignSystem-levelintegrationlayoutNoviolationMemorymoduleFunctionalmodelTestbenchRTLcoding&simulationRTLcodeCellLibrarysynthesisviewRTL-synthesis(DesignCompiler)NetlistphysicalviewPlace&Route(Apollo)LayoutviolationPost-LayoutTimingCheck(DesignTime)SDFSDF:standarddelayformat2023/4/2453 DesignStylesStandardCell(CellBased)EachcellhasequalheightICservicecompanyprovidescelllibrary(forspecificfab.com.):500~1200cellsDesignrule+AbuttingruleCell1Cell2Space/2DCCBACCDCDBBCCCCellMetal1Metal2FeedthroughGNDVDDCDABCelllibrary2023/4/2454 2023/4/2455 集成电路将如何发展？未来的25年内，CMOS技术仍将保持其主流技术地位；SystemonChip(SOC),系统芯片是发展趋势。2023/4/2456 2023/4/2457 2023/4/2458 2023/4/2459 2023/4/2460 2023/4/2461 2023/4/2462 2023/4/2463 Foundry——国内2023/4/2464 Foundry——台湾地区和境外2023/4/2465 国内设计企业炬力集成电路设计有限公司中星微电子有限公司上海杰得微电子有限公司大唐微电子技术有限公司圣邦微电子有限公司瑞芯微电子有限公司展讯通信（上海）有限公司安凯技术有限公司上海海尔集成电路有限公司北京华虹集成电路设计有限责任公司硅谷数模半导体有限公司中国华大集成电路设计集团有限公司2023/4/2466 国内设计企业华润矽威科技（上海）有限公司深圳艾科创新微电子有限公司智多微电子（上海）有限公司昂宝电子(上海)有限公司晶门科技（深圳）有限公司深圳致芯微电子有限公司深圳市力合微电子有限公司重庆西南集成电路设计有限公司北京思旺电子技术有限公司杭州友旺电子有限公司华亚微电子(上海)有限公司2023/4/2467 国内设计企业苏州华芯微电子有限公司上海富瀚微电子有限公司北京凌讯华业科技有限公司绍兴芯谷科技有限公司北京中科亿芯信息技术有限公司杭州士兰微电子有限公司杭州国芯科技有限公司等等2023/4/2468