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时间:2020-11-05
《超大规模集成电路第九次作业2016秋-段成华.docx》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、Assignment91.Designan8-bitupanddownsynchronouscounterinVHDLwiththefollowingfeatures:(1)Thesameportsareusedforsignalstobeinputtedandoutputted.Theportsarebi-directionallybuffered(three-state).(2)Thecounteriswithanasynchronousresetthatassignsaspecificin
2、itialvalueforcounting.(3)Thecounteriswithasynchronousdataloadcontrolinputforanewvalueofcountingandanenablecontrolinputforallowingtheupanddowncounting.Theloadcontrolinputhasapriorityovertheenablecontrolinput.Thisimpliesthatwhentheloadoperationisinproc
3、essthecounteroperationisprohibited.(4)Somedatatypes,suchasSTD_LOGIC,UNSIGNED,SIGNEDandINTEGER,maybeused.Synthesizethedesign.Createasetofreasonableinputwaveformsforyourdesignandcompletebothbehavioralandpost-place&routesimulationswithinternalsignalsand
4、/orvariablesincludedinwaveformorlistwindows.Solution:代码如下:libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.--
5、libraryUNISIM;--useUNISIM.VComponents.all;entitycount_8_bidirisPort(clk:inSTD_LOGIC;rst:inSTD_LOGIC;load:inSTD_LOGIC;enable:inSTD_LOGIC;cnt:inoutSTD_LOGIC_VECTOR(7downto0));endcount_8_bidir;architectureBehavioralofcount_8_bidirissignalcnt_in:STD_LOGI
6、C_VECTOR(7downto0);signalcnt_out:STD_LOGIC_VECTOR(7downto0);beginpro0:process(oe,cnt_out,cnt)beginif(load='1')thencnt<=(others=>'Z');cnt_in<=cnt;elsecnt<=cnt_out;endif;endprocess;pro1:process(clk,rst)beginif(rst='1')thencnt_out<=(others=>'0');elsifri
7、sing_edge(clk)thenif(load='1')thencnt_out<=cnt_in;elsif(enable='1')thencnt_out<=cnt_out+1;elsecnt_out<=cnt_out-1;endif;endif;endprocess;endBehavioral;解释代码:这里有两个进程,进程0时是用来控制三态门控制的双向端口。当cnt作为输入时(load='1'),把cnt赋给cnt_in(初值装载),然后置cnt为高阻状态;否则,即cnt作为输出时(loa
8、d='0'),把cnt_out(计数器计数输出值)赋给cnt。进程1的作用是:当复位信号rst='1',计数器输出cnt_out为全0,否则在时钟的上升沿检测cnt端口是作为输入还是作为输出,当作为输入时(load='1'),把cnt_in中的数取进来,然后当up_down='0'时,进行加法运算,否则做减法运算,同时可以和进程0配合当load='0',将数值从cnt_out输出到cnt。TestBench代码:LIBRARYieee;USEieee.std_logic_1164.ALL;USE
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