ALTERAFPGA数码管动态显示.docx

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1、效果图：显示内容为No.2089使用QuartusII进行开发，采用“仿时序”风格编写，开发板为黑金ALTERAIV开发板，芯片型号EP4CE6F17C8，代码如下：moduleled_demo(CLK,RSTn,Row_Scan_Sig,Column_Scan_Sig);inputCLK;inputRSTn;output[7:0]Row_Scan_Sig;output[5:0]Column_Scan_Sig;reg[7:0]Row;reg[5:0]Column;reg[28:0]Timer;always@(posedgeCLK)beginif(C

2、ount1>=23'd0&&Count1<23'd100_000)beginColumn<=6'b;Row<=8'b;endelseif(Count1>=23'd100_000&&Count1<23'd200_000)beginColumn<=6'b;Row<=8'b;endelseif(Count1>=23'd200_000&&Count1<23'd300_000)beginColumn<=6'b;Row<=8'b;endelseif(Count1>=23'd300_000&&Count1<23'd400_000)beginColumn<=6'b

3、;Row<=8'b;endelseif(Count1>=23'd400_000&&Count1<23'd450_000)beginColumn<=6'b;Row<=8'b;endelseif(Count1>=23'd450_000&&Count1<23'd500_000)beginColumn<=6'b;Row<=8'b;endend/************************************/assignRow_Scan_Sig=Row;assignColumn_Scan_Sig=Column;/******************

4、************************/parameterT10MS=23'd500_000;//晶振为50MHz，50M*0.001=500_000/*************************************/reg[22:0]Count1;always@(posedgeCLKornegedgeRSTn)if(!RSTn)Count1<=23'd0;elseif(Count1==T10MS)Count1<=23'd0;elseCount1<=Count1+1'b1;Endmodule引脚配置如下：