2、_out; input clk_in; input reset; reg [1:0] cnt; reg clk_out;lways@(posedge clk_in or posedge reset) begin if(reset) begin cnt<=0; clk_out<=0; end else begin if(cnt==) begin clk_out<=!clk_out; cnt<=0; end else cnt<=cnt+1; end end endmodule 系统时钟为50MHz,用Ve