北交模拟试卷.doc

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1、BeijingJiaotongUniversityFinalExaminationCourse:ComputerArchitectureLecturer:AiLihua，WangBing（NOTE：4partsin2hours:total100points）PartNo.Part1Part2Part3Part4Part5TotalScoreExaminerPleaseshowyourworkCLEARLYforallproblems.Ihopeyouenjoythetest!Part1—Markonlyoneanswerf

2、oreachquestion[10points]1.Asuperscalarprocessorhas()(a)multiplefunctionalunits(b)ahighclockspeed(c)alargeamountofRAM(d)manyI/Oports2.On-chipcachehas()(a)loweraccesstimethanRAM(b)largercapacitythanoffchipcache(c)itsowndatabus(d)becomeobsolete3.()datahazardsarenotpo

3、ssibleintheDLXin-orderinstructionissueandin-orderexecutionmulticyclepipeline?(a)WAR(b)WAW(c)RAW(d)RAR4.PipeliningimprovesCPUperformancedueto()(a)reducedmemoryaccesstime(b)increasedclockspeed(c)theintroductionofparallellism(d)additionalfunctionalunits5.Cachememorye

4、nhances()(a)memorycapacity(b)memoryaccesstime(c)secondarystoragecapacity(d)secondarystorageaccesstime6.RISCmachinestypically()(a)havehighcapacityon-chipcachememories(b)havefewerregistersthanCISCmachines(c)arelessreliablethanCISCmachines(d)execute1instructionperclo

5、ckcycle.7.WhichofthefollowingisNOTacomputerperformancemetric:()(a)MIPS(b)FLOPS(c)SPECbenchmark,(d)RISC8.Givena5stagepipelinewithstagestaking1,2,3,1,1unitsoftime,theclockperiodofthepipelineis:()(a)8(b)1/8(c)1/3(d)39.Theaveragememoryaccesstimeforamachinewithacachehi

6、trateof90%wherethecacheaccesstimeis10nsandthememoryaccesstimeis100nsis()(a)55ns(b)45ns(c)90ns(d)19ns10.Delayedbranchingisused()(a)tointroducedelaysinprogramexecution(b)inpipelining(c)incachememory(d)decodinginstructionsPart2—FundamentalsofComputerDesign[10points]1

7、.[10points]Inmanypracticalapplicationsthatdemandareal-timeresponse,thecomputationalworkloadWisoftenfixed.Asthenumberofprocessorsincreasesinaparallelcomputer,thefixedworkloadisdistributedtomoreprocessorsforparallelexecution.Assume20percentofWmustbeexecutedsequentia

8、lly,and80percentcanbeexecutedby4nodessimultaneously.Whatisafixed-loadspeedup?Part3—InstructionSetArchitecture[20points]2.[8points]Supposethevariablexoft