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1、四位全加器的VHDL设计一位全加器真值表一位全加器的逻辑表达式S=A⊕B⊕CinCo=AB+BCin+ACin其中A,B为要相加的数，Cin为进位输入；S为和，Co是进位输出；Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityfulladderIsPort(Ci,a,b:INstd_logic;s,Co:OUTstd_logic);Endfulladder;Architecturem1Offulladd
2、erIsSignaltmp:std_logic_vector(1downto0);Begintmp<=('0'&a)+b+Ci;s<=tmp(0);Co<=tmp(1);Endm1;一位全加器的数据流（逻辑）描述Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityfulladderisPort(A,B,CI:instd_logic;S,CO:outstd_logic);Endfulladder;Archi
3、tecturedataflowoffulladderisBeginS<=CIxorAxorB;CO<=(AandB)or(CIandA)or(CIandB);Enddataflow;一位全加器的行为描述Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityfulladderisPort(a,b,cin:Inbit;sum,cout:Outbit);Endfulladder;Architecturebehav
4、eOffulladderIsBeginProcess(a,b,cin)BeginIf(aOrbOrcin)=‘0’Thensum<=‘0’;cout<=‘0’;Elsif(aANDbANDcin)=’1’Thensum<=‘1’;cout<=‘1’;Elsif(aXORbXORcin)=’0’Thensum<=‘0’;cout<=‘1’;Elsesum<=‘1’;cout<=‘0’;EndIf;EndProcess;Endbehave;4位全加器的设计，先设计4个1位的全加器，然后将低位的进位输出与高位
5、的进位输入相连，将要进行加法运算的两个4位数的每一位分别作为每一个1位全加器的输入，进行加法运算，所有的1位全加器的输出组成一个4位数，即输入的两个4位数之和，最高位的全加器产生的进位输出即两个4位数求和的进位输出。（如图）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entityadder4IsPort(Cin:INstd_logic;x,y:INstd_logic_vector(3downto0);sum:
6、OUTstd_logic_vector(3downto0);Cout:OUTstd_logic);Endadder4;ArchitectureaxOfadder4IsSignalc:std_logic_vector(0to4);ComponentfulladderPort(Ci,a,b:INstd_logic;s,Co:OUTstd_logic);Endcomponent;Beginc(0)<=Cin;U1:fulladderPortMap(c(0),x(0),y(0),sum(0),c(1));--U
7、1:fulladderPortMap(Ci=>c(0),a=>x(0),b=>y(0),s=>sum(0),Co=>c(1));U2:fulladderPortMap(c(1),x(1),y(1),sum(1),c(2));U3:fulladderPortMap(c(2),x(2),y(2),sum(2),c(3));U4:fulladderPortMap(c(3),x(3),y(3),sum(3),c(4));Cout<=c(4);Endax;libraryieee;useieee.std_logic
8、_1164.all;useieee.std_logic_unsigned.all;entityadder4bitisport(cin:instd_logic;a,b:instd_logic_vector(3downto0);s:outstd_logic_vector(3downto0);cout:outstd_logic);endadder4bit;architecturebehofadder4bitissignalsint:std_log
