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ID:57013508
大小:110.19 KB
页数:4页
时间:2020-07-30
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1、Chapter10SignalMultiplexingandSignalDescriptionsTable10-2.Portcontrolregisterconfigurationsummary(continued)ThisfieldGenerallyExceptforResetstoConfigurabilityofresetstoPORTx_PCRnISF0Noexceptions-allareclearedonreset.—OnlyimplementedforportsthatsupportinterruptandDMAfunctionality.1.T
2、heRESETpinhasthepassiveanalogfilterfixedenabledwhenfunctioningastheRESETpin(FOPT[RESET_PIN_CFG]=1)andfixeddisabledwhenconfiguredforothersharedfunctions.10.2.2ClockgatingTheclocktotheportcontrolmodulecanbegatedonandoffusingtheSCGC5[PORTx]bitsintheSIMmodule.Thesebitsareclearedafterany
3、reset,whichdisablestheclocktothecorrespondingmoduletoconservepower.Priortoinitializingthecorrespondingmodule,setSCGC5[PORTx]intheSIMmoduletoenabletheclock.Beforeturningofftheclock,makesuretodisablethemodule.Formoredetails,refertotheclockdistributionchapter.10.2.3Signalmultiplexingco
4、nstraints1.Agivenperipheralfunctionmustbeassignedtoamaximumofonepackagepin.Donotprogramthesamefunctiontomorethanonepin.2.Toensurethebestsignaltimingforagivenperipheral'sinterface,choosethepinsinclosestproximitytoeachother.10.3Pinout10.3.1KL25SignalMultiplexingandPinAssignmentsThefol
5、lowingtableshowsthesignalsavailableoneachpinandthelocationsofthesepinsonthedevicessupportedbythisdocument.ThePortControlModuleisresponsibleforselectingwhichALTfunctionalityisavailableoneachpin.80644832PinNameDefaultALT0ALT1ALT2ALT3ALT4ALT5ALT6ALT7LQFPLQFPQFNQFN11—1PTE0DISABLEDPTE0UA
6、RT1_TXRTC_CLKOUTCMP0_OUTI2C1_SDA22——PTE1DISABLEDPTE1SPI1_MOSIUART1_RXSPI1_MISOI2C1_SCLKL25Sub-FamilyReferenceManual,Rev.3,September2012FreescaleSemiconductor,Inc.161Pinout80644832PinNameDefaultALT0ALT1ALT2ALT3ALT4ALT5ALT6ALT7LQFPLQFPQFNQFN3———PTE2DISABLEDPTE2SPI1_SCK4———PTE3DISABLED
7、PTE3SPI1_MISOSPI1_MOSI5———PTE4DISABLEDPTE4SPI1_PCS06———PTE5DISABLEDPTE5731—VDDVDDVDD8422VSSVSSVSS9533USB0_DPUSB0_DPUSB0_DP10644USB0_DMUSB0_DMUSB0_DM11755VOUT33VOUT33VOUT3312866VREGINVREGINVREGIN1397—PTE20ADC0_DP0/ADC0_DP0/PTE20TPM1_CH0UART0_TXADC0_SE0ADC0_SE014108—PTE21ADC0_DM0/ADC0
8、_DM0/PTE21TPM1_CH1U
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