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ID:56918999
大小:19.50 KB
页数:3页
时间:2020-07-24
《基于VHDL语言状态机编写流水灯.doc》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、基于VHDL语言状态机编写流水灯采用元件例化方式编写流水灯包含以下三个程序:第一个程序代码如下:libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;--Uncommentthefollowinglibrarydeclarationifusing--arithmeticfunctionswithSignedorUnsignedvalues--useIEEE.NUMERIC_STD.ALL;--Uncommentthefollowinglibrarydeclarationifinstantiating--anyXi
2、linxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entityfenpinisPort(clk:inSTD_LOGIC;clkout:outSTD_LOGIC);endfenpin;architectureBehavioraloffenpinissignalclk1:std_logic:='0';beginprocess(clk)variablecnt:integerrange0to4095;variablecnt1:integerrange0to4
3、095;beginifclk'eventandclk='1'thenifcnt=4095thencnt:=0;clk1<=notclk1;elseifcnt1=4095thencnt1:=0;cnt:=cnt+1;elsecnt1:=cnt1+1;endif;endif;endif;endprocess;clkout<=clk1;endBehavioral;第二个程序代码如下:libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;--Uncommentthefollowinglibrarydeclarationi
4、fusing--arithmeticfunctionswithSignedorUnsignedvalues--useIEEE.NUMERIC_STD.ALL;--Uncommentthefollowinglibrarydeclarationifinstantiating--anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitylightisport(clk:instd_logic;light:outstd_logic_vector(
5、7downto0));endlight;architectureBehavioraloflightistypestate_typeis(a,b,c,d,e,f,g,h);signalstate:state_type;beginprocess(clk)beginifclk'eventandclk='1'thencasestateiswhena=>state<=b;whenb=>state<=c;whenc=>state<=d;whend=>state<=e;whene=>state<=f;whenf=>state<=g;wheng=>st
6、ate<=h;whenothers=>state<=a;endcase;endif;endprocess;process(state)begincasestateiswhena=>light<="";whenb=>light<="";whenc=>light<="";whend=>light<="";whene=>light<="";whenf=>light<="";wheng=>light<="";whenh=>light<="";endcase;endprocess;endBehavioral;第三个程序代码如下:libraryIE
7、EE;useIEEE.STD_LOGIC_1164.ALL;--Uncommentthefollowinglibrarydeclarationifusing--arithmeticfunctionswithSignedorUnsignedvalues--useIEEE.NUMERIC_STD.ALL;--Uncommentthefollowinglibrarydeclarationifinstantiating--anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VCom
8、ponents.all;entitylight_fisPort(clk:inSTD_LOGIC;light1:outSTD_LOGIC_VECTOR(7downto0));endlight_f;archit
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