FPGA时分秒电子钟24小时计.doc

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1、设计一个具有时、分、秒计时的电子钟，按24小时计时。要求：（1）数字钟的时间用六位数码管分别显示时、分、秒；（2）用两个控制键，对数字钟分别进行分、时校正；（3）用VerilogHDL语言设计，用Modelsim软件做功能仿真，用QuartusII综合。（4）将设计代码和仿真代码写在作业本上。modulecountersmh(out,sel,dp,clock_128,clear,corr_min,corr_hour);inputclock_128,clear,corr_min,corr_hour;output[6:0]out;output[2:0]sel;outputdp;reg[6:0]o

2、ut;reg[2:0]sel;reg[3:0]cnt_sl,cnt_sh,cnt_ml,cnt_mh,cnt_hl,cnt_hh,count;reg[15:0]fenping;wireclock_1=fenping[1];always@(posedgeclock_128ornegedgeclear)beginif(!clear)fenping<=16'b0;elsefenping<=fenping+1;end//cnt_slalways@(posedgeclock_1ornegedgeclear)beginif(!clear)cnt_sl<=4'b0;elseif(cnt_sl==9)cnt

3、_sl<=4'b0;elsecnt_sl<=cnt_sl+1;end//cnt_shalways@(posedgeclock_1ornegedgeclear)beginif(!clear)cnt_sh<=4'b0;elseif(cnt_sh==5&&cnt_sl==9)cnt_sh<=4'b0;elseif(cnt_sl==9)cnt_sh<=cnt_sh+1;elsecnt_sh<=cnt_sh;end//cnt_mlalways@(posedgeclock_1ornegedgeclear)beginif(!clear)cnt_ml<=4'b0;elseif(cnt_sh==5&&cnt_

4、sl==9&&cnt_ml==9)cnt_ml<=4'b0;elseif(corr_min==0)beginif(cnt_ml==9)cnt_ml<=4'b0;elsecnt_ml<=cnt_ml+1;endelseif(cnt_sh==5&&cnt_sl==9)cnt_ml<=cnt_ml+1;elsecnt_ml<=cnt_ml;end//cnt_mhalways@(posedgeclock_1ornegedgeclear)beginif(!clear)cnt_mh<=4'b0;elseif(cnt_sh==5&&cnt_sl==9&&cnt_ml==9&&cnt_mh==5)cnt_m

5、h<=4'b0;elseif(corr_min==0)beginif(cnt_mh==5&&cnt_ml==9)cnt_mh<=4'b0;elseif(cnt_ml==9)cnt_mh<=cnt_mh+1;elsecnt_mh<=cnt_mh;endelseif(cnt_sh==5&&cnt_sl==9&&cnt_ml==9)cnt_mh<=cnt_mh+1;elsecnt_mh<=cnt_mh;end//cnt_hlalways@(posedgeclock_1ornegedgeclear)beginif(!clear)cnt_hl<=4'b0;elseif(cnt_hh==2&&cnt_h

6、l==3&&cnt_mh==5&&cnt_ml==9&&cnt_sh==5&&cnt_sl==9)cnt_hl<=4'b0;elseif(cnt_hl==9&&cnt_mh==5&&cnt_ml==9&&cnt_sh==5&&cnt_sl==9)cnt_hl<=4'b0;elseif(corr_hour==0)beginif(cnt_hh==2&&cnt_hl==3)cnt_hl<=4'b0;elseif(cnt_hl==9)cnt_hl<=4'b0;elsecnt_hl<=cnt_hl+1;endelseif(cnt_mh==5&&cnt_ml==9&&cnt_sh==5&&cnt_sl=

7、=9)cnt_hl<=cnt_hl+1;elsecnt_hl<=cnt_hl;end//cnt_hhalways@(posedgeclock_1ornegedgeclear)beginif(!clear)cnt_hh<=4'b0;elseif(cnt_hh==2&&cnt_hl==3&&cnt_mh==5&&cnt_ml==9&&cnt_sh==5&&cnt_sl==9)cnt_hh<=4'b0;elseif