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ID:55296549
大小:426.50 KB
页数:13页
时间:2020-05-09
《基于VHDL语言的数字钟设计.doc》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、一.程序代码及其仿真:1.cnt60子模块代码:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYV_cnt60ISPORT(clk:INstd_logic;Q0,Q1,Q2,Q3,Q4,Q5,Q6,QC:OUTstd_logic);ENDV_cnt60;ARCHITECTUREfuncOFV_cnt60ISSIGNALcount1:std_logic_vector(3downto0);SIGNALcount2:std_logic_vector(3downt
2、o0);SIGNALcarryin:std_logic;BEGINQ0<=count1(0);Q1<=count1(1);Q2<=count1(2);Q3<=count1(3);Q4<=count2(0);Q5<=count2(1);Q6<=count2(2);QC<=carryin;process(clk)BEGINif(clk'eventANDclk='1')thencarryin<='0';if(count1="1001")thencount1<="0000";count2<=count2+1;elsecount1<=count1+1;ENDif;if
3、(count2="0101"ANDcount1="1001")thencount2<="0000";count1<="0000";carryin<='1';ENDif;ENDif;ENDprocess;ENDfunc;cnt60仿真波形:1.cnt24子模块代码:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYV_cnt24ISPORT(clk:INstd_logic;Q0,Q1,Q2,Q3,Q4,Q5:OUTstd_logic);ENDV_cnt24;A
4、RCHITECTUREfunc_cnt24OFV_cnt24ISSIGNALcount1:std_logic_vector(3downto0);SIGNALcount2:std_logic_vector(3downto0);SIGNALcarryin:std_logic;BEGINQ0<=count1(0);Q1<=count1(1);Q2<=count1(2);Q3<=count1(3);Q4<=count2(0);Q5<=count2(1);process(clk)BEGINif(clk'eventandclk='1')thenif(count1="10
5、01")thencount1<="0000";count2<=count2+1;elsecount1<=count1+1;ENDif;if(count2="0010"ANDcount1="0011")thencount2<="0000";count1<="0000";ENDif;ENDif;ENDprocess;ENDfunc_cnt24;cnt24仿真波形:1.cnt1000字模块代码:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityV_cnt1000i
6、sport(clk:instd_logic;cnt1000:outstd_logic;clk_c:outstd_logic);endV_cnt1000;architecturebhvofV_cnt1000issignaltmp:std_logic_vector(9downto0);signalamp:std_logic_vector(8downto0);beginprocess(clk)beginif(clk'eventandclk='1')thenif(tmp=1023)thentmp<="0000000000";elsetmp<=tmp+1;endif;
7、if(tmp<511)thencnt1000<='0';elsecnt1000<='1';endif;endif;endprocess;process(clk)beginif(clk'eventandclk='1')thenif(amp=511)thenamp<="000000000";elseamp<=amp+1;endif;if(amp<255)thenclk_c<='0';elseclk_c<='1';endif;endif;endprocess;endbhv;cnt1000仿真波形:1.clk_c子模块代码:libraryIEEE;useIEEE.s
8、td_logic_1164.all;useIEEE.
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