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1、QuartusII与Modelsim仿真的区别：用QuartusII写了一个隔直滤波器，运用QuartusII9.1自带的波形仿真，仿真结果与matlab仿真后的结果比较近似。仿真结果为：下图为testbench部分代码：LIBRARYieee;USEieee.std_logic_1164.all;useIEEE.STD_LOGIC_ARITH.ALL;useieee.std_logic_unsigned.all;useieee.std_logic_signed.all;ENTITYgezhi_filter_vhd_tstISENDgezhi_filter_vhd_tst;A
2、RCHITECTUREgezhi_filter_archOFgezhi_filter_vhd_tstISconstantclk_period:time:=10ns;--constants--signals);ENDCOMPONENT;BEGINi1:gezhi_filterPORTMAP(--listconnectionsbetweenmasterportsandsignalsclk,clr,d00,d02,d04,d06,d11,d22,d_sf0,d_sf10,d_sf20,d_sf30,d_sf40,d_sf120,d_sf340,din_x,dou_y);clk_ge
3、n:PROCESS--variabledeclarationsBEGINclk<='0';--codethatexecutesonlyoncewaitforclk_period/2;clk<='1';waitforclk_period/2;ENDPROCESS;clr_gen:PROCESSBEGIN--clr<='1';--codeexecutesforeveryeventonsensitivitylist--waitforclk_period/4;clr<='0';WAIT;ENDPROCESS;din_x_gen:PROCESSBEGINdin_x<=CONV_STD_
4、LOGIC_VECTOR(256,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(-12,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(32,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(39,18);--codethatexecutesonlyoncewai
5、tforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(-128,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(512,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(520,18);--codethatexecutesonlyoncewaitforclk_period;din_x<=CONV_STD_LOGIC_VECTOR(15,
6、18);--codethatexecutesonlyoncewaitforclk_period;ENDPROCESS;ENDgezhi_filter_arch;调用modelsim6.5SE仿真后的波形图：仿真结果中，din_x是输入，dou_y是输出，modelsim结果中的红线X代表未知输出而不是0，导致最后的结果dou_y开头都是0输出，和Quartus仿真结果不同。解决办法：加上上电复位，开始是clr=1全部清零。Testbench里clr激励更改如下：clr_gen:PROCESSBEGINclr<='1';--codeexecutesforeveryeventon
7、sensitivitylistwaitforclk_period/4;clr<='0';WAIT;ENDPROCESS;Modelsim仿真结果，dou_y已经和Quartus结果差不多了，但是也略有差别，不知道原因总结：调用QuartusII，端口default值是0，而调用modelsim，端口默认未知X，所以程序一定要先在端口清零，否则导致错误输出。
