ti 高速布局注意事项

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1、HighSpeedLayoutConsiderationsStevenShi(steven-shi@ti.com)TelecomAFATeamTexasInstrumentsAgenda1)GeneralConsiderationsa)Models:Resistors,Capacitors,Inductors,andCircuitBoard2)HighSpeedOpAmpLayouta)Inputandoutputconsiderationsb)Signalroutingc)Bypasscapacitorsd)Layoutex

2、amples3)HighSpeedADC/DACDesignandLayouta)Inputandoutputconsiderationsb)BypassCapacitorsc)SplittingtheGroundPlane4)HighSpeedClockLayoutGuidelinesa)Coupling(InterferenceorCrossTalk)b)PowerSupplyFilteringc)PowerSupplyBypassing&Groundingd)LayoutTrickstoReduceEMIHighSpee

3、dLayoutKeyGeneralConsiderations¾Keypoints–Useshortdirectsignalrouting–Controlparasiticcapacitance–Useadequatelocalbypasscapacitors–Managegroundplanes–AvoidgroundloopsCapacitorModelsIdealModelBetterModelBestModelRCPAR.PAR.CESRESLCESRESLCNOM(Temp,(Temp,Freq,RLEAKVolta

4、ge)ImpedanceVs.FrequencyVoltage)10.00(Voltage)L=1nHC=0.01uF()22ZΩ=(ESR)+(XESL+XC)1.00()XESLΩ=2πLfESLLimitationIdealCapacitor10.10X()Impedance-OhmsCΩ=Z=2PifL2πCfRealCapacitorZ=1/2PifC0.0111101001000fRES=Frequency-MHz2πLCInductorModelsBestModelIdealModelBetterModelRIW

5、CIWCLDCRLDCRRL(Freq,(Temp)Temp)RPARImpedanceVs.Frequency100001RealInductorfRES=2πLC1000IWCLimitationXL(Ω)=2πLfIdealInductorZ=1/2PifCZ=2PifL1Impedance-Ohms100XIWC()Ω=2πCfL=1uHIWC=10pF10XLXIWC1101001000Z()Ω=DCR+Frequency-MHzXL+XIWCResistorModelsIdealModelBetterModelBe

6、stModelCCPackageRPackageLLRLEADRLEAD(Temp)¾UsingSMTresistorsminimizesleadinductancetothepointthatPCBtracesarethelimitingfactor¾SMTpackagesalsominimizethecapacitancebetweentheleadssuchthatthisparasiticisusuallyinsignificant¾NotethatresistorpacksCANhavesignificantlead

7、inductanceandresistor-to-resistorcapacitance,sochoosewiselybasedontheapplication¾Resistorswillhavetemperaturecoefficients,200PPMiscommon,buthigherprecisionisavailable¾AVOIDWire-woundresistorsandleadedresistorsforhighspeedapplicationsduetotheirlargeinductanceRemember

8、CurrentReturnPathI1Owj(A/cm)=×ε2rπh⎛D⎞1+⎜⎟t⎝h⎠hI=totalsignalcurrent(A)j(A/cm)Oh=PCBthickness(cm)D=distancefromcenteroftrace(cm)D¾ReturnCur