NIOSII开发板原理图.pdf

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1、54321REVDESCRIPTIONDATEAPPROVEDNOTES,UNLESSOTHERWISESPECIFIED:0.1Initialschematic10/7/04YaoYuan1.RESISTANCEVALUESINOHMS.0.9ReadyforLayout10/10/04YaoYuan2.CAPACTITANCEVALUESINFARADS.3.ALL0.1uFand0.01uFCAPACITORSAREDDDECOUPLINGCAPSUNLESSOTHERWISENOTED.THEYARESHOWNONTHEPAGEWI

2、THTHEICsANDSHOULDBEPLACEDNEAR.4.BOARDPROPERTIES:A.ROUTETOWITHIN10%OFMANHATTANDISTANCEB.50+/-5OHMMATCHEDINPEDANCEC.OUTERLAYERS0.5OZCU/W0.5OZAUPLATINGD.INNERLAYERS1.0OZCUE.FR4BOARDMATERIALF.MIMIMUMTRACEWIDTH/SPACING6MILS布局参考：（具体尺寸根据实际情况而定）CG.MINIMUMVIASIZE12/20MILSCRESETH.LA

3、YERSTACKUP:ALTERA_ASSDRAMPOWERLT1085-3.3V,LT1585-1.5V1.TOP-SIGNALROUTINGCLOCKPAGE032.GROUNDPLANE13.3.3VPOWERPLANEEXT_ADDRCONFIG_IOALTERA_JTAG4.BOTTOM-SIGNALROUTINGCYCLONEFPGAEP1C1/4EP1C6/EP1C12SRAMSRAMFLASHPQ240BPAGE04BEXT_DATAMAX3232SCHEMATICINDEX:DB9PAGE02LEDsSWITCHEXT_I

4、OLOGO00NOTES01CONNECTORS,UART,LED&OTHERS说明:02CYCLONECLOCK,PLL&RESET1.采用四层板设计，SDRAM的信号处理要注意等长原则，FPGA的管脚定义可以适当调整，但是SDCLK的位置不能动；03CYCLONECONFIG2.蓝色边框的单元为接插件，注意与周围器件的间距；右侧为扩展区域，不能有高过8mm的器件；04CYCLONEIO05CYCLONEPOWER06SYSTEMPOWERA07SDRAMA08SRAMTitleRedCycloneMainBoard09FLASHSize

5、DocumentNumberRevA42004001ADate:Wednesday,November03,2004Sheet11of05432154321EA[19:0]EA[19:0]ED[31:0]5VED[31:0]5V5VJE1JE2JE312EA0EA13412DEA6EA5ED7ED612DEA456EA3ED534ED4ECLKIN_P34ECLKIN_N7856ECLKIN_PECLKIN_NEA2EA16ED3ED256910ED178ED0ECLKOUT_P78ECLKOUT_N1112910ECLKOUT_PECLKO

6、UT_NEA15EA14910EA131314EA12ED151112ED14EGPIO01112EGPIO1EA171516EA18ED131314ED12EGPIO21314EGPIO3pack1:EA191718EA7ED111516ED10EGPIO41516EGPIO5EA15-FLASH_RY_BY#1920ED91718ED8EGPIO61718EGPIO721221920FLASH_RY_BY#2324SYS_RST#2122EGPIO81920EGPIO9ED23ED222122FLASH_RW#2526ED212324E

7、D20EGPIO102324EGPIO11EA82728EA9ED192526ED18EGPIO122526EGPIO132930ED172728ED16EGPIO142728EGPIO15EA103132EA112930293033343132ED31ED30FLASH_CE#3536SYS_RSTFLASH_OE#ED293334ED28FLASH_BYTE#3738SYS_RST3536ED27ED26EXT_IO39403738ED25ED243940EXT_ADDRCEXT_DATA【D】CEGPIO[15:0]3.3V3.3VE

8、GPIO[15:0]RD1RD2RD3RD44.7K4.7K4.7K4.7K3.3VSW[1:0]SW1SWITCHCU10.1uFU100CU20.1uFRS232PORTSW