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1、.2-28moduleadder_4(cout,sum,ina,inb,cin,clk);output[3:0]sum;outputcout;input[3:0]Ina,inb;//tempa,tempb中间变量声明inputcin,clk;reg[3:0]tempa,tempb,sum;regcout;regtempc;//tempc中间变量声明always@(posedgeclk)//alwaysclk上升沿触发begin//阻塞语句tempa=ina;tempb=inb;tempc=cin;endalways@(posedgecl
2、k)//alwaysclk上升沿触发begin{cout,sum}=tempa+tempb+tempc;endendmodule2-40`timescale1ns/10psmoduleadder4_testbench;reg[3:0]ina,inb;regcin;regclk=0;wire[3:0]sum;wirecout;always#10clk=~clk;initialbeginina=0;repeat(20)#20ina=$random;//随机数ina产生endinitialbegininb=0;repeat(10)#40inb
3、=$random;//随机数inb产生endinitialbegincin=0;repeat(2)#200cin={$random}%16;//随机数inc产生#200$stop;页脚.endadder4adder4_te(.clk(clk),.sum(sum),.cout(cout),.ina(ina),.inb(inb),.cin(cin));initialendmodule2-73LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY
4、SEG_7ISPORT(SEG:INSTD_LOGIC_VECTOR(3DOWNTO0);//--四位二进制码输入Q3:OUTSTD_LOGIC_VECTOR(6DOWNTO0));//--输出LED七段码ENDSEG_7;ARCHITECTUREARTOFSEG_7ISBEGINPROCESS(SEG)BEGINCASESEGISWHEN"0000"=>Q3<="0000001";--0WHEN"0001"=>Q3<="1001111";--1WHEN"0010"=>Q3<="0010010";--2WHEN"0011"=>Q3<="
5、0000110";--3WHEN"0100"=>Q3<="1001100";--4WHEN"0101"=>Q3<="0100100";--5WHEN"0110"=>Q3<="0100000";--6WHEN"0111"=>Q3<="0001111";--7WHEN"1000"=>Q3<="0000000";--8WHEN"1001"=>Q3<="0000100";--9WHENOTHERS=>Q3<="1111111";ENDCASE;ENDPROCESS;ENDART;3-1`timescale1ns/1nsmoduleDecoder
6、2x4(A,B,EN,Z);inputA,B,EN;output[0:3]Z;wireAbar,Bbar;assign#1Abar=~A;//语句1assign#1Bbar=~B;//语句2assign#2Z[0]=~(Abar&Bbar&EN);//语句3assign#2Z[1]=~(Abar&B&EN);//语句4assign#2Z[2]=~(A&Bbar&EN);//语句5页脚.assign#2Z[3]=~(A&B&EN);//语句6endmodule3-3moduleFASeq(A,B,Cin,Sum,Cout);inputA,
7、B,Cin;outputSum,Cout;regSum,Cout;regT1,T2,T3;always@(AorBorCin)beginSum=(A^B)^Cin;T1=A&Cin;T2=B&Cin;T3=A&B;Cout=(T1
8、T2)
9、T3;endendmodule3-4`timescale1ns/1nsmoduleTest(Pop,Pid);outputPop,Pid;regPop,Pid;initialbeginPop=0;//语句1Pid=0;//语句2Pop=#51;//语句3Pid=#31;//语句4Pop=#60;//语
10、句5Pid=#20;//语句6endendmodule3-5ModuleFourBitFA(FA,FB,FCin,FSum,FCout);parameterSIZE=4;input[SIZE:1]FA,FB