QuartusII时序优化策略.ppt

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1、QuartusIISoftwareDesignSeries:OptimizationOptimizationTechniques–TimingOptimizationTimingOptimizationGeneralRecommendationsAnalyzingTimingFailuresSolvingTypicalTimingFailures2GeneralRecommendationsClocksI/OAsynchronousControlSignalsManyofthesesuggestionsarefoundinTimingOptimizationAdvisor&Q

2、uartusIIHandbook3ClocksOptimizeforSpeedApplygloballyApplyhierarchicallyApplytospecificclockdomainEnablenetlistoptimizationsEnablephysicalsynthesis4GlobalSpeedOptimizationSelectspeedDefaultisbalancedArea-optimizeddesignsmayalsoshowspeedimprovementsMayresultinincreasedlogicresourceusage5Indiv

3、idualOptimizationOptimizationTechniquelogicoptionUseAssignmentEditororTcltoapplytohierarchicalblockSpeedOptimizationTechniqueforClockDomainslogicoptionUseAssignmentEditororTcltoapplytoclockdomainorbetweenclockdomains6SynthesisNetlistOptimizationsFurtheroptimizenetlistsduringsynthesisTypesWY

4、SIWYGprimitiveresynthesisGate-levelregisterretimingCreated/modifiednodesnotedinCompilationReport7WYSIWYGPrimitiveResynthesisUnmaps3rd-partyatomnetlistbacktogates&thenremapstoAlteraprimitivesNotintendedforusewithintegratedsynthesisConsiderationsNodenamesmaychange3rd-partysynthesisattributesm

5、aybelostPreserve/keepSomeregistersmaybesynthesizedaway8Gate-LevelRegisterRetimingMovesregistersacrosscombinatoriallogictobalancetimingTradesbetweencritical&non-criticalpathsMakeschangesatgatelevel9PhysicalSynthesisRe-synthesisbasedonfitteroutputMakesincrementalchangesthatimproveresultsforag

6、ivenplacementCompensatesforroutingdelaysfromfitter10PhysicalSynthesisTypesTargetingperformance:CombinationallogicAsynchronoussignalpipeliningRegisterduplicationRegisterretimingTargetingfittingPhysicalsynthesisforcombinatoriallogicLogictomemorymappingEffortTradesperformancevs.compiletimeNorm

7、al,extraorfastNewormodifiednodesappearinCompilationReport11CombinationalLogicSwapslook-uptable(LUT)portswithinLEstoreducecriticalpathLEsfgab-criticalLUTLUTcdeLUTLUTfgaecdb12AsynchronousControlSignalsImproveRecovery&RemovalTimingMakecontrolsignalnon-globa